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| 1 /* |
| 2 * Copyright (c) 2011 The Chromium OS Authors. |
| 3 * See file CREDITS for list of people who contributed to this |
| 4 * project. |
| 5 * |
| 6 * This program is free software; you can redistribute it and/or |
| 7 * modify it under the terms of the GNU General Public License as |
| 8 * published by the Free Software Foundation; either version 2 of |
| 9 * the License, or (at your option) any later version. |
| 10 * |
| 11 * This program is distributed in the hope that it will be useful, |
| 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 * GNU General Public License for more details. |
| 15 * |
| 16 * You should have received a copy of the GNU General Public License |
| 17 * along with this program; if not, write to the Free Software |
| 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 * MA 02111-1307 USA |
| 20 */ |
| 21 |
| 22 /* Tegra2 clock control functions */ |
| 23 |
| 24 #ifndef _CLOCK_H |
| 25 |
| 26 |
| 27 /* Set of oscillator frequencies supported in the internal API. */ |
| 28 enum clock_osc_freq { |
| 29 /* All in MHz, so 13_0 is 13.0MHz */ |
| 30 CLOCK_OSC_FREQ_13_0, |
| 31 CLOCK_OSC_FREQ_19_2, |
| 32 CLOCK_OSC_FREQ_12_0, |
| 33 CLOCK_OSC_FREQ_26_0, |
| 34 |
| 35 CLOCK_OSC_FREQ_COUNT, |
| 36 }; |
| 37 |
| 38 /* The PLLs supported by the hardware */ |
| 39 enum clock_pll_id { |
| 40 CLOCK_PLL_ID_FIRST, |
| 41 CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST, |
| 42 CLOCK_PLL_ID_MEMORY, |
| 43 CLOCK_PLL_ID_PERIPH, |
| 44 CLOCK_PLL_ID_AUDIO, |
| 45 CLOCK_PLL_ID_USB, |
| 46 CLOCK_PLL_ID_DISPLAY, |
| 47 |
| 48 /* now the simple ones */ |
| 49 CLOCK_PLL_ID_FIRST_SIMPLE, |
| 50 CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE, |
| 51 CLOCK_PLL_ID_EPCI, |
| 52 CLOCK_PLL_ID_SFROM32KHZ, |
| 53 |
| 54 CLOCK_PLL_ID_COUNT, |
| 55 }; |
| 56 |
| 57 /* The clocks supported by the hardware */ |
| 58 enum periph_id { |
| 59 PERIPH_ID_FIRST, |
| 60 |
| 61 /* Low word: 31:0 */ |
| 62 PERIPH_ID_CPU = PERIPH_ID_FIRST, |
| 63 PERIPH_ID_RESERVED1, |
| 64 PERIPH_ID_RESERVED2, |
| 65 PERIPH_ID_AC97, |
| 66 PERIPH_ID_RTC, |
| 67 PERIPH_ID_TMR, |
| 68 PERIPH_ID_UART1, |
| 69 PERIPH_ID_UART2, |
| 70 |
| 71 /* 8 */ |
| 72 PERIPH_ID_GPIO, |
| 73 PERIPH_ID_SDMMC2, |
| 74 PERIPH_ID_SPDIF, |
| 75 PERIPH_ID_I2S1, |
| 76 PERIPH_ID_I2C1, |
| 77 PERIPH_ID_NDFLASH, |
| 78 PERIPH_ID_SDMMC1, |
| 79 PERIPH_ID_SDMMC4, |
| 80 |
| 81 /* 16 */ |
| 82 PERIPH_ID_TWC, |
| 83 PERIPH_ID_PWC, |
| 84 PERIPH_ID_I2S2, |
| 85 PERIPH_ID_EPP, |
| 86 PERIPH_ID_VI, |
| 87 PERIPH_ID_2D, |
| 88 PERIPH_ID_USBD, |
| 89 PERIPH_ID_ISP, |
| 90 |
| 91 /* 24 */ |
| 92 PERIPH_ID_3D, |
| 93 PERIPH_ID_IDE, |
| 94 PERIPH_ID_DISP2, |
| 95 PERIPH_ID_DISP1, |
| 96 PERIPH_ID_HOST1X, |
| 97 PERIPH_ID_VCP, |
| 98 PERIPH_ID_RESERVED30, |
| 99 PERIPH_ID_CACHE2, |
| 100 |
| 101 /* Middle word: 63:32 */ |
| 102 PERIPH_ID_MEM, |
| 103 PERIPH_ID_AHBDMA, |
| 104 PERIPH_ID_APBDMA, |
| 105 PERIPH_ID_RESERVED35, |
| 106 PERIPH_ID_KBC, |
| 107 PERIPH_ID_STAT_MON, |
| 108 PERIPH_ID_PMC, |
| 109 PERIPH_ID_FUSE, |
| 110 |
| 111 /* 40 */ |
| 112 PERIPH_ID_KFUSE, |
| 113 PERIPH_ID_SBC1, |
| 114 PERIPH_ID_SNOR, |
| 115 PERIPH_ID_SPI1, |
| 116 PERIPH_ID_SBC2, |
| 117 PERIPH_ID_XIO, |
| 118 PERIPH_ID_SBC3, |
| 119 PERIPH_ID_DVC_I2C, |
| 120 |
| 121 /* 48 */ |
| 122 PERIPH_ID_DSI, |
| 123 PERIPH_ID_TVO, |
| 124 PERIPH_ID_MIPI, |
| 125 PERIPH_ID_HDMI, |
| 126 PERIPH_ID_CSI, |
| 127 PERIPH_ID_TVDAC, |
| 128 PERIPH_ID_I2C2, |
| 129 PERIPH_ID_UART3, |
| 130 |
| 131 /* 56 */ |
| 132 PERIPH_ID_RESERVED56, |
| 133 PERIPH_ID_EMC, |
| 134 PERIPH_ID_USB2, |
| 135 PERIPH_ID_USB3, |
| 136 PERIPH_ID_MPE, |
| 137 PERIPH_ID_VDE, |
| 138 PERIPH_ID_BSEA, |
| 139 PERIPH_ID_BSEV, |
| 140 |
| 141 /* Upper word 95:64 */ |
| 142 PERIPH_ID_SPEEDO, |
| 143 PERIPH_ID_UART4, |
| 144 PERIPH_ID_UART5, |
| 145 PERIPH_ID_I2C3, |
| 146 PERIPH_ID_SBC4, |
| 147 PERIPH_ID_SDMMC3, |
| 148 PERIPH_ID_PCIE, |
| 149 PERIPH_ID_OWR, |
| 150 |
| 151 /* 72 */ |
| 152 PERIPH_ID_AFI, |
| 153 PERIPH_ID_CORESIGHT, |
| 154 PERIPH_ID_RESERVED74, |
| 155 PERIPH_ID_AVPUCQ, |
| 156 PERIPH_ID_RESERVED76, |
| 157 PERIPH_ID_RESERVED77, |
| 158 PERIPH_ID_RESERVED78, |
| 159 PERIPH_ID_RESERVED79, |
| 160 |
| 161 /* 80 */ |
| 162 PERIPH_ID_RESERVED80, |
| 163 PERIPH_ID_RESERVED81, |
| 164 PERIPH_ID_RESERVED82, |
| 165 PERIPH_ID_RESERVED83, |
| 166 PERIPH_ID_IRAMA, |
| 167 PERIPH_ID_IRAMB, |
| 168 PERIPH_ID_IRAMC, |
| 169 PERIPH_ID_IRAMD, |
| 170 |
| 171 /* 88 */ |
| 172 PERIPH_ID_CRAM2, |
| 173 |
| 174 PERIPH_ID_COUNT, |
| 175 }; |
| 176 |
| 177 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ |
| 178 #define PERIPH_REG(id) ((id) >> 5) |
| 179 |
| 180 /* Mask value for a clock (within PERIPH_REG(id)) */ |
| 181 #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) |
| 182 |
| 183 /* return 1 if a PLL ID is in range */ |
| 184 #define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \ |
| 185 (id) < CLOCK_PLL_ID_COUNT) |
| 186 |
| 187 /* return 1 if a peripheral ID is in range */ |
| 188 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ |
| 189 (id) < PERIPH_ID_COUNT) |
| 190 |
| 191 /* PLL stabilization delay in usec */ |
| 192 #define CLOCK_PLL_STABLE_DELAY_US 300 |
| 193 |
| 194 /* return the current oscillator clock frequency */ |
| 195 enum clock_osc_freq clock_get_osc_freq(void); |
| 196 |
| 197 /* |
| 198 * Start PLL using the provided configuration parameters. |
| 199 * |
| 200 * @param id clock id |
| 201 * @param divm input divider |
| 202 * @param divn feedback divider |
| 203 * @param divp post divider 2^n |
| 204 * @param cpcon charge pump setup control |
| 205 * @param lfcon loop filter setup control |
| 206 * |
| 207 * @returns monotonic time in us that the PLL will be stable |
| 208 */ |
| 209 unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, |
| 210 u32 divp, u32 cpcon, u32 lfcon); |
| 211 |
| 212 /* |
| 213 * Enable a clock |
| 214 * |
| 215 * @param id clock id |
| 216 */ |
| 217 void clock_enable(enum periph_id clkid); |
| 218 |
| 219 /* |
| 220 * Set whether a clock is enabled or disabled. |
| 221 * |
| 222 * @param id clock id |
| 223 * @param enable 1 to enable, 0 to disable |
| 224 */ |
| 225 void clock_set_enable(enum periph_id clkid, int enable); |
| 226 |
| 227 /* |
| 228 * Reset a peripheral. This puts it in reset, waits for a delay, then takes |
| 229 * it out of reset and waits for th delay again. |
| 230 * |
| 231 * @param periph_id peripheral to reset |
| 232 * @param us_delay time to delay in microseconds |
| 233 */ |
| 234 void reset_periph(enum periph_id periph_id, int us_delay); |
| 235 |
| 236 /* |
| 237 * Put a peripheral into or out of reset. |
| 238 * |
| 239 * @param periph_id peripheral to reset |
| 240 * @param enable 1 to put into reset, 0 to take out of reset |
| 241 */ |
| 242 void reset_set_enable(enum periph_id periph_id, int enable); |
| 243 |
| 244 |
| 245 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ |
| 246 enum crc_reset_id { |
| 247 /* Things we can hold in reset for each CPU */ |
| 248 crc_rst_cpu = 1, |
| 249 crc_rst_de = 1 << 2, /* What is de? */ |
| 250 crc_rst_watchdog = 1 << 3, |
| 251 crc_rst_debug = 1 << 4, |
| 252 }; |
| 253 |
| 254 /* |
| 255 * Put parts of the CPU complex into or out of reset.\ |
| 256 * |
| 257 * @param cpu cpu number (0 or 1 on Tegra2) |
| 258 * @param which which parts of the complex to affect (OR of crc_reset_id
) |
| 259 * @param reset 1 to assert reset, 0 to de-assert |
| 260 */ |
| 261 void reset_cmplx_set_enable(int cpu, int which, int reset); |
| 262 |
| 263 #endif |
| 264 |
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