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| 1 /* |
| 2 * Copyright (c) 2011 The Chromium OS Authors. |
| 3 * See file CREDITS for list of people who contributed to this |
| 4 * project. |
| 5 * |
| 6 * This program is free software; you can redistribute it and/or |
| 7 * modify it under the terms of the GNU General Public License as |
| 8 * published by the Free Software Foundation; either version 2 of |
| 9 * the License, or (at your option) any later version. |
| 10 * |
| 11 * This program is distributed in the hope that it will be useful, |
| 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 * GNU General Public License for more details. |
| 15 * |
| 16 * You should have received a copy of the GNU General Public License |
| 17 * along with this program; if not, write to the Free Software |
| 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 * MA 02111-1307 USA |
| 20 */ |
| 21 |
| 22 /* Tegra2 Clock control functions */ |
| 23 |
| 24 #include <asm/io.h> |
| 25 #include <asm/arch/bitfield.h> |
| 26 #include <asm/arch/clk_rst.h> |
| 27 #include <asm/arch/clock.h> |
| 28 #include <asm/arch/timer.h> |
| 29 #include <asm/arch/tegra2.h> |
| 30 #include <common.h> |
| 31 |
| 32 #ifdef DEBUG |
| 33 #define assert(x) \ |
| 34 ({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \ |
| 35 #x, __FILE__, __LINE__); }) |
| 36 #else |
| 37 #define assert(x) |
| 38 #endif |
| 39 |
| 40 /* |
| 41 * Get the oscillator frequency, from the corresponding hardware configuration |
| 42 * field. |
| 43 */ |
| 44 enum clock_osc_freq clock_get_osc_freq(void) |
| 45 { |
| 46 struct clk_rst_ctlr *clkrst = |
| 47 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
| 48 u32 reg; |
| 49 |
| 50 reg = readl(&clkrst->crc_osc_ctrl); |
| 51 return bf_unpack(OSC_FREQ, reg); |
| 52 } |
| 53 |
| 54 unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, |
| 55 u32 divp, u32 cpcon, u32 lfcon) |
| 56 { |
| 57 struct clk_rst_ctlr *clkrst = |
| 58 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
| 59 u32 data; |
| 60 struct clk_pll *pll; |
| 61 |
| 62 assert(clock_pll_id_isvalid(clkid)); |
| 63 pll = &clkrst->crc_pll[clkid]; |
| 64 |
| 65 /* |
| 66 * We cheat by treating all PLL (except PLLU) in the same fashion. |
| 67 * This works only because: |
| 68 * - same fields are always mapped at same offsets, except DCCON |
| 69 * - DCCON is always 0, doesn't conflict |
| 70 * - M,N, P of PLLP values are ignored for PLLP |
| 71 */ |
| 72 |
| 73 data = bf_pack(PLL_CPCON, cpcon) | |
| 74 bf_pack(PLL_LFCON, lfcon); |
| 75 writel(data, &pll->pll_misc); |
| 76 |
| 77 data = bf_pack(PLL_DIVM, divm) | |
| 78 bf_pack(PLL_DIVN, divn) | |
| 79 bf_pack(PLL_BYPASS, 0) | |
| 80 bf_pack(PLL_ENABLE, 1); |
| 81 |
| 82 if (clkid == CLOCK_PLL_ID_USB) |
| 83 data |= bf_pack(PLL_VCO_FREQ, divp); |
| 84 else |
| 85 data |= bf_pack(PLL_DIVP, divp); |
| 86 writel(data, &pll->pll_base); |
| 87 |
| 88 /* calculate the stable time */ |
| 89 return timer_get_future_us(CLOCK_PLL_STABLE_DELAY_US); |
| 90 } |
| 91 |
| 92 void clock_set_enable(enum periph_id periph_id, int enable) |
| 93 { |
| 94 struct clk_rst_ctlr *clkrst = |
| 95 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
| 96 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; |
| 97 u32 reg; |
| 98 |
| 99 /* Enable/disable the clock to this peripheral */ |
| 100 assert(clock_periph_id_isvalid(periph_id)); |
| 101 reg = readl(clk); |
| 102 if (enable) |
| 103 reg |= PERIPH_MASK(periph_id); |
| 104 else |
| 105 reg &= ~PERIPH_MASK(periph_id); |
| 106 writel(reg, clk); |
| 107 } |
| 108 |
| 109 void clock_enable(enum periph_id clkid) |
| 110 { |
| 111 clock_set_enable(clkid, 1); |
| 112 } |
| 113 |
| 114 void clock_disable(enum periph_id clkid) |
| 115 { |
| 116 clock_set_enable(clkid, 0); |
| 117 } |
| 118 |
| 119 void reset_set_enable(enum periph_id periph_id, int enable) |
| 120 { |
| 121 struct clk_rst_ctlr *clkrst = |
| 122 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
| 123 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; |
| 124 u32 reg; |
| 125 |
| 126 /* Enable/disable reset to the peripheral */ |
| 127 assert(clock_periph_id_isvalid(periph_id)); |
| 128 reg = readl(reset); |
| 129 if (enable) |
| 130 reg |= PERIPH_MASK(periph_id); |
| 131 else |
| 132 reg &= ~PERIPH_MASK(periph_id); |
| 133 writel(reg, reset); |
| 134 } |
| 135 |
| 136 void reset_periph(enum periph_id periph_id, int us_delay) |
| 137 { |
| 138 /* Put peripheral into reset */ |
| 139 reset_set_enable(periph_id, 1); |
| 140 udelay(us_delay); |
| 141 |
| 142 /* Remove reset */ |
| 143 reset_set_enable(periph_id, 0); |
| 144 |
| 145 udelay(us_delay); |
| 146 } |
| 147 |
| 148 void reset_cmplx_set_enable(int cpu, int which, int reset) |
| 149 { |
| 150 struct clk_rst_ctlr *clkrst = |
| 151 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
| 152 u32 mask; |
| 153 |
| 154 /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */ |
| 155 assert(cpu >= 0 && cpu < 2); |
| 156 mask = which << cpu; |
| 157 |
| 158 /* either enable or disable those reset for that CPU */ |
| 159 if (reset) |
| 160 writel(mask, &clkrst->crc_cpu_cmplx_set); |
| 161 else |
| 162 writel(mask, &clkrst->crc_cpu_cmplx_clr); |
| 163 } |
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