Tegra2: Add more clock support

arch/arm/cpu/armv7/tegra2/ap20.c

 /*
 * (C) Copyright 2010-2011
 * NVIDIA Corporation <www.nvidia.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 
 #include "ap20.h"
 #include <asm/io.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/pmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/scu.h>
 #include <common.h>
 
 u32 s_first_boot = 1;
 
 void init_pllx(void)
 {
         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+        struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU];
         u32 reg;
 
         /* If PLLX is already enabled, just return */
-        reg = readl(&clkrst->crc_pllx_base);
-        if (reg & PLL_ENABLE)
+        reg = readl(&pll->pll_base);
+        if (reg & PLL_ENABLE_BIT)
                 return;
 
         /* Set PLLX_MISC */
         reg = CPCON;                            /* CPCON[11:8]  = 0001 */
-        writel(reg, &clkrst->crc_pllx_misc);
+        writel(reg, &pll->pll_misc);
 
         /* Use 12MHz clock here */
-        reg = (PLL_BYPASS | PLL_DIVM);
+        reg = (PLL_BYPASS_BIT | PLL_DIVM_VALUE);
         reg |= (1000 << 8);                     /* DIVN = 0x3E8 */
-        writel(reg, &clkrst->crc_pllx_base);
+        writel(reg, &pll->pll_base);
 
-        reg |= PLL_ENABLE;
-        writel(reg, &clkrst->crc_pllx_base);
+        reg |= PLL_ENABLE_BIT;
+        writel(reg, &pll->pll_base);
 
-        reg &= ~PLL_BYPASS;
-        writel(reg, &clkrst->crc_pllx_base);
+        reg &= ~PLL_BYPASS_BIT;
+        writel(reg, &pll->pll_base);
 }
 
 static void enable_cpu_clock(int enable)
 {
         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-        u32 reg, clk;
+        u32 clk;
 
         /*
          * NOTE:
          * Regardless of whether the request is to enable or disable the CPU
          * clock, every processor in the CPU complex except the master (CPU 0)
          * will have it's clock stopped because the AVP only talks to the
          * master. The AVP does not know (nor does it need to know) that there
          * are multiple processors in the CPU complex.
          */
 
         if (enable) {
                 /* Initialize PLLX */
                 init_pllx();
 
                 /* Wait until all clocks are stable */
                 udelay(PLL_STABILIZATION_DELAY);
 
                 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
                 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
         }
 
-        /* Fetch the register containing the main CPU complex clock enable */
-        reg = readl(&clkrst->crc_clk_out_enb_l);
-        reg |= CLK_ENB_CPU;
-
         /*
          * Read the register containing the individual CPU clock enables and
          * always stop the clock to CPU 1.
          */
         clk = readl(&clkrst->crc_clk_cpu_cmplx);
         clk |= CPU1_CLK_STP;
 
         if (enable) {
                 /* Unstop the CPU clock */
                 clk &= ~CPU0_CLK_STP;
         } else {
                 /* Stop the CPU clock */
                 clk |= CPU0_CLK_STP;
         }
 
         writel(clk, &clkrst->crc_clk_cpu_cmplx);
-        writel(reg, &clkrst->crc_clk_out_enb_l);
+        clock_enable(PERIPH_ID_CPU);
 }
 
 static int is_cpu_powered(void)
 {
         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
         return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
@@ skipping 55 matching lines @@
          * the power rail and enabling the CPU clock.  This delay
          * between SM1EN and SM1 is for switching time + the ramp
          * up of the voltage to the CPU (VDD_CPU from PMU).
          */
         udelay(3750);
 }
 
 static void reset_A9_cpu(int reset)
 {
         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-        u32 reg, cpu;
+        u32 cpu;
 
         /*
         * NOTE:  Regardless of whether the request is to hold the CPU in reset
         *        or take it out of reset, every processor in the CPU complex
         *        except the master (CPU 0) will be held in reset because the
         *        AVP only talks to the master. The AVP does not know that there
         *        are multiple processors in the CPU complex.
         */
 
         /* Hold CPU 1 in reset */
         cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
         writel(cpu, &clkrst->crc_cpu_cmplx_set);
 
-        reg = readl(&clkrst->crc_rst_dev_l);
         if (reset) {
                 /* Now place CPU0 into reset */
                 cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
                 writel(cpu, &clkrst->crc_cpu_cmplx_set);
-
-                /* Enable master CPU reset */
-                reg |= SWR_CPU_RST;
         } else {
                 /* Take CPU0 out of reset */
                 cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
                 writel(cpu, &clkrst->crc_cpu_cmplx_clr);
-
-                /* Disable master CPU reset */
-                reg &= ~SWR_CPU_RST;
         }
 
-        writel(reg, &clkrst->crc_rst_dev_l);
+        /* Enable/Disable master CPU reset */
+        reset_set_enable(PERIPH_ID_CPU, reset);
 }
 
 static void clock_enable_coresight(int enable)
 {
         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-        u32 rst, clk, src;
+        u32 rst, src;
 
-        rst = readl(&clkrst->crc_rst_dev_u);
-        clk = readl(&clkrst->crc_clk_out_enb_u);
-
-        if (enable) {
-                rst &= ~SWR_CSITE_RST;
-                clk |= CLK_ENB_CSITE;
-        } else {
-                rst |= SWR_CSITE_RST;
-                clk &= ~CLK_ENB_CSITE;
-        }
-
-        writel(clk, &clkrst->crc_clk_out_enb_u);
-        writel(rst, &clkrst->crc_rst_dev_u);
+        clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+        reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
 
         if (enable) {
                 /*
                  * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
                  *  1.5, giving an effective frequency of 144MHz.
                  * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
                  *  (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
                  */
                 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
                 writel(src, &clkrst->crc_clk_src_csite);
@@ skipping 105 matching lines @@
         }
 
 #ifdef CONFIG_ENABLE_CORTEXA9
         /* take the mpcore out of reset */
         cpu_start();
 
         /* configure cache */
         cache_configure();
 #endif
 }