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1 /* | 1 /* |
2 * (C) Copyright 2010,2011 | 2 * (C) Copyright 2010,2011 |
3 * NVIDIA Corporation <www.nvidia.com> | 3 * NVIDIA Corporation <www.nvidia.com> |
4 * | 4 * |
5 * See file CREDITS for list of people who contributed to this | 5 * See file CREDITS for list of people who contributed to this |
6 * project. | 6 * project. |
7 * | 7 * |
8 * This program is free software; you can redistribute it and/or | 8 * This program is free software; you can redistribute it and/or |
9 * modify it under the terms of the GNU General Public License as | 9 * modify it under the terms of the GNU General Public License as |
10 * published by the Free Software Foundation; either version 2 of | 10 * published by the Free Software Foundation; either version 2 of |
11 * the License, or (at your option) any later version. | 11 * the License, or (at your option) any later version. |
12 * | 12 * |
13 * This program is distributed in the hope that it will be useful, | 13 * This program is distributed in the hope that it will be useful, |
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of | 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 * GNU General Public License for more details. | 16 * GNU General Public License for more details. |
17 * | 17 * |
18 * You should have received a copy of the GNU General Public License | 18 * You should have received a copy of the GNU General Public License |
19 * along with this program; if not, write to the Free Software | 19 * along with this program; if not, write to the Free Software |
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
21 * MA 02111-1307 USA | 21 * MA 02111-1307 USA |
22 */ | 22 */ |
23 | 23 |
24 #ifndef _CLK_RST_H_ | 24 #ifndef _CLK_RST_H_ |
25 #define _CLK_RST_H_ | 25 #define _CLK_RST_H_ |
26 | 26 |
27 | |
28 /* PLL registers - there are several PLLs in the clock controller */ | |
29 struct clk_pll { | |
30 uint pll_base; /* the control register */ | |
31 uint pll_out; /* output control */ | |
32 uint reserved; | |
33 uint pll_misc; /* other misc things */ | |
34 }; | |
35 | |
36 /* PLL registers - there are several PLLs in the clock controller */ | |
37 struct clk_pll_simple { | |
38 uint pll_base; /* the control register */ | |
39 uint pll_misc; /* other misc things */ | |
40 }; | |
41 | |
42 /* | |
43 * Most PLLs use the clk_pll structure, but some have a simpler two-member | |
44 * structure for which we use clk_pll_simple. The reason for this non- | |
45 * othogonal setup is not stated. | |
46 */ | |
47 #define TEGRA_CLK_PLLS 6 | |
48 #define TEGRA_CLK_SIMPLE_PLLS 3 /* The number of simple PLLs */ | |
49 #define TEGRA_CLK_REGS 3 /* The number of clock enable registers */ | |
50 | |
Tom Warren
2011/04/26 18:15:32
I'd like to see the values (6, 3, 3) lined up w/ta
sjg
2011/04/26 21:24:32
Done.
| |
27 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ | 51 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ |
28 struct clk_rst_ctlr { | 52 struct clk_rst_ctlr { |
29 » uint crc_rst_src;» » /* _RST_SOURCE_0,» 0x00 */ | 53 » uint crc_rst_src;» » /* _RST_SOURCE_0,» 0x00 */ |
30 » uint crc_rst_dev_l;» » /* _RST_DEVICES_L_0,» 0x04 */ | 54 » uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ |
31 » uint crc_rst_dev_h;» » /* _RST_DEVICES_H_0,» 0x08 */ | 55 » uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ |
Tom Warren
2011/04/26 18:15:32
Ditto. Line up comments.
sjg
2011/04/26 21:24:32
Have done as best I can given line length limitati
| |
32 » uint crc_rst_dev_u;» » /* _RST_DEVICES_U_0,» 0x0C */ | |
33 » uint crc_clk_out_enb_l;»» /* _CLK_OUT_ENB_L_0,» 0x10 */ | |
34 » uint crc_clk_out_enb_h;»» /* _CLK_OUT_ENB_H_0,» 0x14 */ | |
35 » uint crc_clk_out_enb_u;»» /* _CLK_OUT_ENB_U_0,» 0x18 */ | |
36 uint crc_reserved0; /* reserved_0, 0x1C */ | 56 uint crc_reserved0; /* reserved_0, 0x1C */ |
37 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ | 57 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ |
38 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ | 58 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ |
39 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ | 59 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ |
40 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ | 60 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ |
41 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ | 61 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ |
42 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ | 62 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ |
43 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ | 63 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ |
44 uint crc_reserved1; /* reserved_1, 0x3C */ | 64 uint crc_reserved1; /* reserved_1, 0x3C */ |
45 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ | 65 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ |
46 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ | 66 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ |
47 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ | 67 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ |
48 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ | 68 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ |
49 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ | 69 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ |
50 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ | 70 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ |
51 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ | 71 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ |
52 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ | 72 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ |
53 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ | 73 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ |
54 | 74 |
55 » uint crc_pllc_base;» » /* _PLLC_BASE_0,» 0x80 */ | 75 » struct clk_pll crc_pll[TEGRA_CLK_PLLS];»/* PLLs from 0x80 to 0xdc */ |
56 » uint crc_pllc_out;» » /* _PLLC_OUT_0,»» 0x84 */ | |
57 » uint crc_reserved3;» » /* reserved_3,» » 0x88 */ | |
58 » uint crc_pllc_misc;» » /* _PLLC_MISC_0,» 0x8C */ | |
59 | 76 |
60 » uint crc_pllm_base;» » /* _PLLM_BASE_0,» 0x90 */ | 77 » /* PLLs from 0xe0 to 0xf4 */ |
61 » uint crc_pllm_out;» » /* _PLLM_OUT_0,»» 0x94 */ | 78 » struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; |
62 » uint crc_reserved4;» » /* reserved_4,» » 0x98 */ | |
63 » uint crc_pllm_misc;» » /* _PLLM_MISC_0,» 0x9C */ | |
64 | 79 |
65 uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0 */ | |
66 uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4 */ | |
67 uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8 */ | |
68 uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC */ | |
69 | |
70 uint crc_plla_base; /* _PLLA_BASE_0, 0xB0 */ | |
71 uint crc_plla_out; /* _PLLA_OUT_0, 0xB4 */ | |
72 uint crc_reserved5; /* reserved_5, 0xB8 */ | |
73 uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC */ | |
74 | |
75 uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0 */ | |
76 uint crc_reserved6; /* _reserved_6, 0xC4 */ | |
77 uint crc_reserved7; /* _reserved_7, 0xC8 */ | |
78 uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC */ | |
79 | |
80 uint crc_plld_base; /* _PLLD_BASE_0, 0xD0 */ | |
81 uint crc_reserved8; /* _reserved_8, 0xD4 */ | |
82 uint crc_reserved9; /* _reserved_9, 0xD8 */ | |
83 uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC */ | |
84 | |
85 uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0 */ | |
86 uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4 */ | |
87 | |
88 uint crc_plle_base; /* _PLLE_BASE_0, 0xE8 */ | |
89 uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC */ | |
90 | |
91 uint crc_plls_base; /* _PLLS_BASE_0, 0xF0 */ | |
92 uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4 */ | |
93 uint crc_reserved10; /* _reserved_10, 0xF8 */ | 80 uint crc_reserved10; /* _reserved_10, 0xF8 */ |
94 uint crc_reserved11; /* _reserved_11, 0xFC */ | 81 uint crc_reserved11; /* _reserved_11, 0xFC */ |
95 | 82 |
96 uint crc_clk_src_i2s1; /*_I2S1_0, 0x100 */ | 83 uint crc_clk_src_i2s1; /*_I2S1_0, 0x100 */ |
97 uint crc_clk_src_i2s2; /*_I2S2_0, 0x104 */ | 84 uint crc_clk_src_i2s2; /*_I2S2_0, 0x104 */ |
98 uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108 */ | 85 uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108 */ |
99 uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C */ | 86 uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C */ |
100 uint crc_clk_src_pwm; /*_PWM_0, 0x110 */ | 87 uint crc_clk_src_pwm; /*_PWM_0, 0x110 */ |
101 uint crc_clk_src_spi1; /*_SPI1_0, 0x114 */ | 88 uint crc_clk_src_spi1; /*_SPI1_0, 0x114 */ |
102 uint crc_clk_src_sbc2; /*_SBC2_0, 0x118 */ | 89 uint crc_clk_src_sbc2; /*_SBC2_0, 0x118 */ |
(...skipping 44 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
147 uint crc_clk_src_owr; /*_OWR_0, 0x1CC */ | 134 uint crc_clk_src_owr; /*_OWR_0, 0x1CC */ |
148 uint crc_clk_src_nor; /*_NOR_0, 0x1D0 */ | 135 uint crc_clk_src_nor; /*_NOR_0, 0x1D0 */ |
149 uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */ | 136 uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */ |
150 uint crc_reserved19[9]; /* 0x1D8-1F8 */ | 137 uint crc_reserved19[9]; /* 0x1D8-1F8 */ |
151 uint crc_clk_src_osc; /*_OSC_0, 0x1FC */ | 138 uint crc_clk_src_osc; /*_OSC_0, 0x1FC */ |
152 uint crc_reserved20[80]; /* 0x200-33C */ | 139 uint crc_reserved20[80]; /* 0x200-33C */ |
153 uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ | 140 uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ |
154 uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ | 141 uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ |
155 }; | 142 }; |
156 | 143 |
157 #define PLL_BYPASS» » (1 << 31) | 144 #define PLL_BYPASS_BIT» » (1 << 31) |
158 #define PLL_ENABLE» » (1 << 30) | 145 #define PLL_ENABLE_BIT» » (1 << 30) |
159 #define PLL_BASE_OVRRIDE» (1 << 28) | 146 #define PLL_BASE_OVRRIDE_BIT» (1 << 28) |
160 #define PLL_DIVP» » (1 << 20)» /* post divider, b22:20 */ | 147 #define PLL_DIVP_VALUE» » (1 << 20)» /* post divider, b22:20 */ |
161 #define PLL_DIVM» » 0x0C» » /* input divider, b4:0 */ | 148 #define PLL_DIVM_VALUE» » 0x0C» » /* input divider, b4:0 */ |
162 | 149 |
163 #define SWR_UARTD_RST (1 << 1) | 150 #define SWR_UARTD_RST (1 << 1) |
164 #define CLK_ENB_UARTD (1 << 1) | 151 #define CLK_ENB_UARTD (1 << 1) |
165 #define SWR_UARTA_RST (1 << 6) | 152 #define SWR_UARTA_RST (1 << 6) |
166 #define CLK_ENB_UARTA (1 << 6) | 153 #define CLK_ENB_UARTA (1 << 6) |
167 | 154 |
168 #define SWR_CPU_RST (1 << 0) | 155 #define SWR_CPU_RST (1 << 0) |
169 #define CLK_ENB_CPU (1 << 0) | 156 #define CLK_ENB_CPU (1 << 0) |
170 #define SWR_CSITE_RST (1 << 9) | 157 #define SWR_CSITE_RST (1 << 9) |
171 #define CLK_ENB_CSITE (1 << 9) | 158 #define CLK_ENB_CSITE (1 << 9) |
(...skipping 12 matching lines...) Expand all Loading... | |
184 | 171 |
185 #define CLR_CPURESET1 (1 << 1) | 172 #define CLR_CPURESET1 (1 << 1) |
186 #define CLR_DERESET1 (1 << 5) | 173 #define CLR_DERESET1 (1 << 5) |
187 #define CLR_DBGRESET1 (1 << 13) | 174 #define CLR_DBGRESET1 (1 << 13) |
188 | 175 |
189 #define CPU0_CLK_STP (1 << 8) | 176 #define CPU0_CLK_STP (1 << 8) |
190 #define CPU1_CLK_STP (1 << 9) | 177 #define CPU1_CLK_STP (1 << 9) |
191 | 178 |
192 #define CPCON (1 << 8) | 179 #define CPCON (1 << 8) |
193 | 180 |
181 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */ | |
182 #define PLL_BYPASS_RANGE 31:31 | |
183 #define PLL_ENABLE_RANGE 30:30 | |
184 #define PLL_BASE_OVRRIDE_RANGE 28:28 | |
185 #define PLL_DIVP_RANGE 22:20 | |
186 #define PLL_DIVN_RANGE 17:8 | |
187 #define PLL_DIVM_RANGE 4:0 | |
188 | |
189 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */ | |
190 #define PLL_CPCON_RANGE 11:8 | |
191 #define PLL_LFCON_RANGE 7:4 | |
192 #define PLLU_VCO_FREQ_RANGE 20:20 | |
193 #define PLL_VCO_FREQ_RANGE 3:0 | |
194 | |
195 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ | |
196 #define OSC_FREQ_RANGE 31:30 | |
197 | |
194 #endif /* CLK_RST_H */ | 198 #endif /* CLK_RST_H */ |
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