Do not call EC programmer shutdown functions explicitly.

it85spi.c

Index: it85spi.c
diff --git a/it85spi.c b/it85spi.c
index 2493c1f66cbd2364ce15326a397974a5c1221f3f..03cdaacd09932761963b1d9c29c97b3c925af457 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -260,6 +260,12 @@ void it85xx_exit_scratch_rom()
 	}
 }
 
+static void it85xx_shutdown(void *data)
+{
+	msg_pdbg("%s():%d\n", __func__, __LINE__);
+	it85xx_exit_scratch_rom();
+}
+
 int it85xx_spi_common_init(void)
 {
 	chipaddr base;
@@ -269,6 +275,9 @@ int it85xx_spi_common_init(void)
 	if (superio.vendor != SUPERIO_VENDOR_ITE)
 		return 1;
 
+	if (register_shutdown(it85xx_shutdown, NULL))
+		return 1;
+
 #ifdef LPC_IO
 	/* Get LPCPNP of SHM. That's big-endian */
 	sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
@@ -300,7 +309,6 @@ int it85xx_spi_common_init(void)
 
 	/* Set this as spi controller. */
 	spi_controller = SPI_CONTROLLER_IT85XX;
-
 	return 0;
 }
 
@@ -342,13 +350,6 @@ int it85xx_probe_spi_flash(const char *name)
 	return ret;
 }
 
-int it85xx_shutdown(void)
-{
-	msg_pdbg("%s():%d\n", __func__, __LINE__);
-	it85xx_exit_scratch_rom();
-	return 0;
-}
-
 /* According to ITE 8502 document, the procedure to follow mode is following:
  *   1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
  *   2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI