Do not call EC programmer shutdown functions explicitly.

it85spi.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
  * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
  * Copyright (C) 2008 coresystems GmbH
  * Copyright (C) 2010 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ skipping 61 matching lines @@
 #ifdef LPC_IO
 /* macro to fill in indirect-access registers. */
 #define INDIRECT_A0(base, value) OUTB(value, (base) + 0)  /* little-endian */
 #define INDIRECT_A1(base, value) OUTB(value, (base) + 1)
 #define INDIRECT_A2(base, value) OUTB(value, (base) + 2)
 #define INDIRECT_A3(base, value) OUTB(value, (base) + 3)
 #define INDIRECT_READ(base) INB((base) + 4)
 #define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4)
 #endif  /* LPC_IO */
 
+void it85xx_shutdown(void *);
+
 #ifdef LPC_IO
 unsigned int shm_io_base;
 #endif
 unsigned char *ce_high, *ce_low;
 static int it85xx_scratch_rom_reenter = 0;
 
 uint16_t probe_id_ite85(uint16_t port)
 {
         uint16_t id;
 
@@ skipping 202 matching lines @@
                                                      0x1000);
         msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
                  (unsigned int)base);
         ce_high = (unsigned char*)(base + 0xE00);  /* 0xFFFFFE00 */
         ce_low = (unsigned char*)(base + 0xD00);  /* 0xFFFFFD00 */
 #endif
 
         /* Set this as spi controller. */
         spi_controller = SPI_CONTROLLER_IT85XX;
 
+        register_shutdown(it85xx_shutdown, NULL);
         return 0;
 }
 
 /* Called by programmer_entry .init */
 int it85xx_spi_init(void)
 {
         int ret;
 
         get_io_perms();
         /* Probe for the Super I/O chip and fill global struct superio. */
@@ skipping 21 matching lines @@
         if (!ret) {
                 msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
                           buses_supported);
                 if (buses_supported & CHIP_BUSTYPE_FWH)
                         msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
                 buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
         }
         return ret;
 }
 
-int it85xx_shutdown(void)
+void it85xx_shutdown(void *data)
 {
         msg_pdbg("%s():%d\n", __func__, __LINE__);
         it85xx_exit_scratch_rom();
-        return 0;
 }
 
 /* According to ITE 8502 document, the procedure to follow mode is following:
  *   1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
  *   2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
  *      with data)
  *   3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
  *      data from MISO)
  */
 int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
@@ skipping 34 matching lines @@
         INDIRECT_WRITE(shm_io_base, 0xFF);  /* Write anything to this address.*/
 #endif
 #ifdef LPC_MEMORY
         *ce_high = 0;
 #endif
 
         return 0;
 }
 
 #endif