Do not call EC programmer shutdown functions explicitly.

it85spi.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
  * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
  * Copyright (C) 2008 coresystems GmbH
  * Copyright (C) 2010 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ skipping 242 matching lines @@
 
         /* FIXME: this a workaround for the bug that SMBus signal would
          *        interfere the EC firmware update. Should be removed if
          *        we find out the root cause. */
         ret = system("start powerd >&2");
         if (ret) {
                 msg_perr("Cannot start powerd again.\n");
         }
 }
 
+static void it85xx_shutdown(void *data)
+{
+        msg_pdbg("%s():%d\n", __func__, __LINE__);
+        it85xx_exit_scratch_rom();
+}
+
 int it85xx_spi_common_init(void)
 {
         chipaddr base;
 
         msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
                  superio.vendor);
         if (superio.vendor != SUPERIO_VENDOR_ITE)
                 return 1;
 
+        if (register_shutdown(it85xx_shutdown, NULL))
+                return 1;
+
 #ifdef LPC_IO
         /* Get LPCPNP of SHM. That's big-endian */
         sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
         shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) +
                       sio_read(superio.port, SHM_IO_BAD1);
         msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
                  shm_io_base);
 
         /* These pointers are not used directly. They will be send to EC's
          * register for indirect access. */
@@ skipping 11 matching lines @@
         base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000,
                                                      0x1000);
         msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
                  (unsigned int)base);
         ce_high = (unsigned char*)(base + 0xE00);  /* 0xFFFFFE00 */
         ce_low = (unsigned char*)(base + 0xD00);  /* 0xFFFFFD00 */
 #endif
 
         /* Set this as spi controller. */
         spi_controller = SPI_CONTROLLER_IT85XX;
-
         return 0;
 }
 
 /* Called by programmer_entry .init */
 int it85xx_spi_init(void)
 {
         int ret;
 
         get_io_perms();
         /* Probe for the Super I/O chip and fill global struct superio. */
@@ skipping 21 matching lines @@
         if (!ret) {
                 msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
                           buses_supported);
                 if (buses_supported & CHIP_BUSTYPE_FWH)
                         msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
                 buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
         }
         return ret;
 }
 
-int it85xx_shutdown(void)
-{
-        msg_pdbg("%s():%d\n", __func__, __LINE__);
-        it85xx_exit_scratch_rom();
-        return 0;
-}
-
 /* According to ITE 8502 document, the procedure to follow mode is following:
  *   1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
  *   2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
  *      with data)
  *   3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
  *      data from MISO)
  */
 int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
                         const unsigned char *writearr, unsigned char *readarr)
 {
@@ skipping 32 matching lines @@
         INDIRECT_WRITE(shm_io_base, 0xFF);  /* Write anything to this address.*/
 #endif
 #ifdef LPC_MEMORY
         *ce_high = 0;
 #endif
 
         return 0;
 }
 
 #endif