Atomic ops: put the CPU features struct in v8::internal.

src/atomicops_internals_x86_gcc.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 39 matching lines @@
 #elif defined(__x86_64__)
 #define cpuid(a, b, c, d, inp) \
   asm("mov %%rbx, %%rdi\n"     \
       "cpuid\n"                \
       "xchg %%rdi, %%rbx\n"    \
       : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
 #endif
 
 #if defined(cpuid)        // initialize the struct only on x86
 
+namespace v8 {
+namespace internal {
+
 // Set the flags so that code will run correctly and conservatively, so even
 // if we haven't been initialized yet, we're probably single threaded, and our
 // default values should hopefully be pretty safe.
 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
   false,          // bug can't exist before process spawns multiple threads
   false,          // no SSE2
 };
 
+} }  // namespace v8::internal
+
+namespace {
+
 // Initialize the AtomicOps_Internalx86CPUFeatures struct.
-static void AtomicOps_Internalx86CPUFeaturesInit() {
+void AtomicOps_Internalx86CPUFeaturesInit() {
+  using v8::internal::AtomicOps_Internalx86CPUFeatures;
+
   uint32_t eax;
   uint32_t ebx;
   uint32_t ecx;
   uint32_t edx;
 
   // Get vendor string (issue CPUID with eax = 0)
   cpuid(eax, ebx, ecx, edx, 0);
   char vendor[13];
   memcpy(vendor, &ebx, 4);
   memcpy(vendor + 4, &edx, 4);
@@ skipping 20 matching lines @@
       32 <= model && model <= 63) {
     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
   } else {
     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
   }
 
   // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
   AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
 }
 
-namespace {
-
 class AtomicOpsx86Initializer {
  public:
   AtomicOpsx86Initializer() {
     AtomicOps_Internalx86CPUFeaturesInit();
   }
 };
 
 // A global to get use initialized on startup via static initialization :/
 AtomicOpsx86Initializer g_initer;
 
 }  // namespace
 
 #endif  // if x86
 
 #endif  // ifdef V8_ATOMICOPS_INTERNALS_X86_GCC_H_