Revert MMIO space writes on shutdown as needed.

ichspi.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
  * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
  * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
  * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
  * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
@@ skipping 364 matching lines @@
         /*Program Allowable Opcodes 4 - 7 */
         opmenu[1] = 0;
         for (a = 4; a < 8; a++) {
                 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
         }
 
         msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
         switch (spi_controller) {
         case SPI_CONTROLLER_ICH7:
         case SPI_CONTROLLER_VIA:
-                REGWRITE16(ICH7_REG_PREOP, preop);
-                REGWRITE16(ICH7_REG_OPTYPE, optype);
-                REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
-                REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
+                rmmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
+                rmmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
+                rmmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
+                rmmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
                 break;
         case SPI_CONTROLLER_ICH9:
-                REGWRITE16(ICH9_REG_PREOP, preop);
-                REGWRITE16(ICH9_REG_OPTYPE, optype);
-                REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
-                REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
+                rmmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
+                rmmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
+                rmmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
+                rmmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
                 break;
         default:
                 msg_perr("%s: unsupported chipset\n", __func__);
                 return -1;
         }
 
         return 0;
 }
 
 /*
  * Try to set BBAR (BIOS Base Address Register), but read back the value in case
  * it didn't stick.
  */
 void ich_set_bbar(uint32_t minaddr)
 {
 #define BBAR_MASK       0x00ffff00
         minaddr &= BBAR_MASK;
         switch (spi_controller) {
         case SPI_CONTROLLER_ICH7:
         case SPI_CONTROLLER_VIA:
                 ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK;
                 if (ichspi_bbar)
                         msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
                                  ichspi_bbar);
                 ichspi_bbar |= minaddr;
-                mmio_writel(ichspi_bbar, ich_spibar + 0x50);
+                rmmio_writel(ichspi_bbar, ich_spibar + 0x50);
                 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
-                /* We don't have any option except complaining. */
+                /* We don't have any option except complaining. And if the write
+                 * failed, the restore will fail as well, so no problem there.
+                 */
+
                 if (ichspi_bbar != minaddr)
                         msg_perr("Setting BBAR failed!\n");
                 break;
         case SPI_CONTROLLER_ICH9:
                 ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK;
                 if (ichspi_bbar)
                         msg_pdbg("Reserved bits in BBAR not zero: 0x%04x",
                                  ichspi_bbar);
                 ichspi_bbar |= minaddr;
-                mmio_writel(ichspi_bbar, ich_spibar + 0xA0);
+                rmmio_writel(ichspi_bbar, ich_spibar + 0xA0);
                 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
-                /* We don't have any option except complaining. */
+                /* We don't have any option except complaining. And if the write
+                 * failed, the restore will fail as well, so no problem there.
+                 */
+
                 if (ichspi_bbar != minaddr)
                         msg_perr("Setting BBAR failed!\n");
                 break;
         default:
                 msg_perr("Unknown chipset for BBAR setting!\n");
                 break;
         }
 }
 
 /* This function generates OPCODES from or programs OPCODES to ICH according to
@@ skipping 728 matching lines @@
                 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
                 ichspi_lock = 1;
         }
 
         ich_init_opcodes();
 
         return 0;
 }
 
 #endif