Version 3.2.6

src/mips/constants-mips.cc

Index: src/mips/constants-mips.cc
diff --git a/src/mips/constants-mips.cc b/src/mips/constants-mips.cc
index 49502bdec71484ae3149c0df36d3274818b7285c..16e49c9c8281b665b988543fcb6674c51c0d15d1 100644
--- a/src/mips/constants-mips.cc
+++ b/src/mips/constants-mips.cc
@@ -31,10 +31,8 @@
 
 #include "constants-mips.h"
 
-namespace assembler {
-namespace mips {
-
-namespace v8i = v8::internal;
+namespace v8 {
+namespace internal {
 
 
 // -----------------------------------------------------------------------------
@@ -102,20 +100,20 @@ int Registers::Number(const char* name) {
 }
 
 
-const char* FPURegister::names_[kNumFPURegister] = {
+const char* FPURegisters::names_[kNumFPURegisters] = {
   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11",
   "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
   "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 };
 
 // List of alias names which can be used when referring to MIPS registers.
-const FPURegister::RegisterAlias FPURegister::aliases_[] = {
+const FPURegisters::RegisterAlias FPURegisters::aliases_[] = {
   {kInvalidRegister, NULL}
 };
 
-const char* FPURegister::Name(int creg) {
+const char* FPURegisters::Name(int creg) {
   const char* result;
-  if ((0 <= creg) && (creg < kNumFPURegister)) {
+  if ((0 <= creg) && (creg < kNumFPURegisters)) {
     result = names_[creg];
   } else {
     result = "nocreg";
@@ -124,9 +122,9 @@ const char* FPURegister::Name(int creg) {
 }
 
 
-int FPURegister::Number(const char* name) {
+int FPURegisters::Number(const char* name) {
   // Look through the canonical names.
-  for (int i = 0; i < kNumSimuRegisters; i++) {
+  for (int i = 0; i < kNumFPURegisters; i++) {
     if (strcmp(names_[i], name) == 0) {
       return i;
     }
@@ -149,8 +147,8 @@ int FPURegister::Number(const char* name) {
 // -----------------------------------------------------------------------------
 // Instruction
 
-bool Instruction::IsForbiddenInBranchDelay() {
-  int op = OpcodeFieldRaw();
+bool Instruction::IsForbiddenInBranchDelay() const {
+  const int op = OpcodeFieldRaw();
   switch (op) {
     case J:
     case JAL:
@@ -189,13 +187,18 @@ bool Instruction::IsForbiddenInBranchDelay() {
 }
 
 
-bool Instruction::IsLinkingInstruction() {
-  int op = OpcodeFieldRaw();
+bool Instruction::IsLinkingInstruction() const {
+  const int op = OpcodeFieldRaw();
   switch (op) {
     case JAL:
-    case BGEZAL:
-    case BLTZAL:
-      return true;
+    case REGIMM:
+      switch (RtFieldRaw()) {
+        case BGEZAL:
+        case BLTZAL:
+          return true;
+      default:
+        return false;
+      };
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JALR:
@@ -209,7 +212,7 @@ bool Instruction::IsLinkingInstruction() {
 }
 
 
-bool Instruction::IsTrap() {
+bool Instruction::IsTrap() const {
   if (OpcodeFieldRaw() != SPECIAL) {
     return false;
   } else {
@@ -264,6 +267,9 @@ Instruction::Type Instruction::InstructionType() const {
         case TLTU:
         case TEQ:
         case TNE:
+        case MOVZ:
+        case MOVN:
+        case MOVCI:
           return kRegisterType;
         default:
           UNREACHABLE();
@@ -272,13 +278,23 @@ Instruction::Type Instruction::InstructionType() const {
     case SPECIAL2:
       switch (FunctionFieldRaw()) {
         case MUL:
+        case CLZ:
           return kRegisterType;
         default:
           UNREACHABLE();
       };
       break;
-    case COP1:    // Coprocessor instructions
+    case SPECIAL3:
       switch (FunctionFieldRaw()) {
+        case INS:
+        case EXT:
+          return kRegisterType;
+        default:
+          UNREACHABLE();
+      };
+      break;
+    case COP1:    // Coprocessor instructions
+      switch (RsFieldRawNoAssert()) {
         case BC1:   // branch on coprocessor condition
           return kImmediateType;
         default:
@@ -304,10 +320,17 @@ Instruction::Type Instruction::InstructionType() const {
     case BLEZL:
     case BGTZL:
     case LB:
+    case LH:
+    case LWL:
     case LW:
     case LBU:
+    case LHU:
+    case LWR:
     case SB:
+    case SH:
+    case SWL:
     case SW:
+    case SWR:
     case LWC1:
     case LDC1:
     case SWC1:
@@ -323,6 +346,7 @@ Instruction::Type Instruction::InstructionType() const {
   return kUnsupported;
 }
 
-} }   // namespace assembler::mips
+
+} }   // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS