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Unified Diff: src/arm/code-stubs-arm.cc

Issue 6756033: ARM: Add optimization for constant RHS in DoMulI (try 2) (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 9 months ago
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Index: src/arm/code-stubs-arm.cc
===================================================================
--- src/arm/code-stubs-arm.cc (revision 7433)
+++ src/arm/code-stubs-arm.cc (working copy)
@@ -3445,9 +3445,11 @@
// DIV just falls through to allocating a heap number.
}
+ __ bind(&return_heap_number);
+ // Return a heap number, or fall through to type transition or runtime
+ // call if we can't.
if (result_type_ >= (op_ == Token::DIV) ? TRBinaryOpIC::HEAP_NUMBER
: TRBinaryOpIC::INT32) {
- __ bind(&return_heap_number);
// We are using vfp registers so r5 is available.
heap_number_result = r5;
GenerateHeapResultAllocation(masm,
@@ -3610,7 +3612,11 @@
UNREACHABLE();
}
- if (transition.is_linked()) {
+ // We never expect DIV to yield an integer result, so we always generate
+ // type transition code for DIV operations expecting an integer result: the
+ // code will fall through to this type transition.
+ if (transition.is_linked() ||
+ ((op_ == Token::DIV) && (result_type_ <= TRBinaryOpIC::INT32))) {
__ bind(&transition);
GenerateTypeTransition(masm);
}
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