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Issue 6756033: ARM: Add optimization for constant RHS in DoMulI (try 2) (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 8 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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287 Condition cond) { 287 Condition cond) {
288 if (!src2.is_reg() && 288 if (!src2.is_reg() &&
289 !src2.must_use_constant_pool() && 289 !src2.must_use_constant_pool() &&
290 src2.immediate() == 0) { 290 src2.immediate() == 0) {
291 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond); 291 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond);
292 292
293 } else if (!src2.is_single_instruction() && 293 } else if (!src2.is_single_instruction() &&
294 !src2.must_use_constant_pool() && 294 !src2.must_use_constant_pool() &&
295 Isolate::Current()->cpu_features()->IsSupported(ARMv7) && 295 Isolate::Current()->cpu_features()->IsSupported(ARMv7) &&
296 IsPowerOf2(src2.immediate() + 1)) { 296 IsPowerOf2(src2.immediate() + 1)) {
297 ubfx(dst, src1, 0, WhichPowerOf2(src2.immediate() + 1), cond); 297 ubfx(dst, src1, 0,
298 WhichPowerOf2(static_cast<uint32_t>(src2.immediate()) + 1), cond);
298 299
299 } else { 300 } else {
300 and_(dst, src1, src2, LeaveCC, cond); 301 and_(dst, src1, src2, LeaveCC, cond);
301 } 302 }
302 } 303 }
303 304
304 305
305 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, 306 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width,
306 Condition cond) { 307 Condition cond) {
307 ASSERT(lsb < 32); 308 ASSERT(lsb < 32);
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2942 void CodePatcher::EmitCondition(Condition cond) { 2943 void CodePatcher::EmitCondition(Condition cond) {
2943 Instr instr = Assembler::instr_at(masm_.pc_); 2944 Instr instr = Assembler::instr_at(masm_.pc_);
2944 instr = (instr & ~kCondMask) | cond; 2945 instr = (instr & ~kCondMask) | cond;
2945 masm_.emit(instr); 2946 masm_.emit(instr);
2946 } 2947 }
2947 2948
2948 2949
2949 } } // namespace v8::internal 2950 } } // namespace v8::internal
2950 2951
2951 #endif // V8_TARGET_ARCH_ARM 2952 #endif // V8_TARGET_ARCH_ARM
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