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1 /* | |
2 * (C) Copyright 2010 | |
3 * NVIDIA Corporation <www.nvidia.com> | |
4 * | |
5 * See file CREDITS for list of people who contributed to this | |
6 * project. | |
7 * | |
8 * This program is free software; you can redistribute it and/or | |
9 * modify it under the terms of the GNU General Public License as | |
10 * published by the Free Software Foundation; either version 2 of | |
11 * the License, or (at your option) any later version. | |
12 * | |
13 * This program is distributed in the hope that it will be useful, | |
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 * GNU General Public License for more details. | |
17 * | |
18 * You should have received a copy of the GNU General Public License | |
19 * along with this program; if not, write to the Free Software | |
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 * MA 02111-1307 USA | |
22 */ | |
23 | |
24 /* Set clock divisor | |
25 * 7 bits of D and 1 bit of H | |
26 * divisor= (DDDDDDD + 1) + (H x 0.5) | |
27 * clock = original clock / divisor | |
28 * 6 means /4 */ | |
29 #define CONFIG_NAND_CLK_DIVISOR_DDDDDDDH 6 | |
30 | |
31 /* For HYNIX HY27UF4G2B | |
32 * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz | |
33 * to CLK_RST_CONTROLLER_PLLP_BASE_0, | |
34 * 216MHz / divisor 4 = 54MHZ | |
35 * 1 clock = 18.5 ns = NAND_CLK_PERIOD | |
36 * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode | |
37 * bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5 | |
38 * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24) | |
39 * similar way for other fields, please refer to reference manual | |
40 */ | |
41 /* Value to be set to NAND_TIMING_0 register, address=70008014h */ | |
42 #define CONFIG_TEGRA2_NAND_TIMING 0x15040001 | |
43 /* Value to be set to NAND_TIMING2_0 register, address=7000801Ch */ | |
44 #define CONFIG_TEGRA2_NAND_TIMING2 0x01 | |
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