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1 /* | |
2 * Copyright (c) 2009, Code Aurora Forum. All rights reserved. | |
3 * | |
4 * (C) Copyright 2002-2005 | |
5 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
6 * (C) Copyright 2002 | |
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 * Marius Groeger <mgroeger@sysgo.de> | |
9 * Gary Jennejohn <gj@denx.de> | |
10 * | |
11 * Configuation settings for the st1q board, based on the Qualcomm | |
12 * QSD8x50 surf board. | |
13 * | |
14 * See file CREDITS for list of people who contributed to this | |
15 * project. | |
16 * | |
17 * This program is free software; you can redistribute it and/or | |
18 * modify it under the terms of the GNU General Public License as | |
19 * published by the Free Software Foundation; either version 2 of | |
20 * the License, or (at your option) any later version. | |
21 * | |
22 * This program is distributed in the hope that it will be useful, | |
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 * GNU General Public License for more details. | |
26 * | |
27 * You should have received a copy of the GNU General Public License | |
28 * along with this program; if not, write to the Free Software | |
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 * MA 02111-1307 USA | |
31 */ | |
32 | |
33 #ifndef __CONFIGS_CHROMEOS_ST1Q_COMMON_H | |
34 #define __CONFIGS_CHROMEOS_ST1Q_COMMON_H | |
35 | |
36 #include <asm/arch/QSD8x50_reg.h> | |
37 #include <asm-armv7Scorpion/armv7Scorpion.h> | |
38 #include <config.h> | |
39 | |
40 #define CONFIG_CHROMEOS_HWID "ARM ST1Q TEST 9468" | |
41 | |
42 #define IO_READ32(addr) (*((volatile unsigned int *) (addr))) | |
43 #define IO_WRITE32(addr, val) (*((volatile unsigned int *) (addr)) = ((unsigned
int) (val))) | |
44 #define IO_READ16(addr) (*((volatile unsigned short *) (addr))) | |
45 #define IO_WRITE16(addr, val) (*((volatile unsigned short *) (addr)) = ((unsign
ed short) (val))) | |
46 #define IO_READ8(addr) (*((volatile char *) (addr))) | |
47 #define IO_WRITE8(addr, val) (*((volatile unsigned char *) (addr)) = ((unsigne
d char) (val))) | |
48 | |
49 /* | |
50 * High Level Configuration Options | |
51 * (easy to change) | |
52 */ | |
53 | |
54 #define CONFIG_STACK_BASE | |
55 | |
56 #define CONFIG_ARCH_CPU_INIT | |
57 | |
58 /* | |
59 * Machine ID for ST1 | |
60 */ | |
61 #define LINUX_MACH_TYPE 2508 | |
62 | |
63 #define CONFIG_SYS_HZ (32768) /* GPT Timer frequency */ | |
64 #define CONFIG_TCXO_HZ 19200000 /* TCX0 frequency */ | |
65 | |
66 #undef CONFIG_SHOW_BOOT_PROGRESS | |
67 | |
68 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
69 #define CONFIG_SETUP_MEMORY_TAGS | |
70 #define CONFIG_INITRD_TAG | |
71 | |
72 /* | |
73 * Enable to pass framebuffer info to kernel | |
74 * but after implementing calc_fbsize() in lcdc.c | |
75 */ | |
76 #define CONFIG_VIDEOFLB_ATAG_NOT_SUPPORTED | |
77 | |
78 #define ATAG_CORE_FLAGS 0x00000001 | |
79 #define ATAG_PAGE_SIZE 0x00001000 | |
80 #define ATAG_CORE_RDEV 0x000000FF | |
81 | |
82 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ | |
83 | |
84 /* Warm boot related constants */ | |
85 #define CONFIG_WARMBOOT_TRUE 0xBAC4F00D | |
86 #define CONFIG_WARMBOOT_FALSE 0x15FA15E2 | |
87 | |
88 /* | |
89 * Address where ATAGs are stored and where bootwedge used to be. | |
90 * 2 words at ATAGs are overwritten by power collapse routine | |
91 * in the kernel to cause a jump back to the | |
92 * power collapse exit routine in the kernel. | |
93 * These are restored back to their original values | |
94 * after successful power collapse . | |
95 */ | |
96 #define CONFIG_WARMBOOT_POWER_COLLAPSE_EXIT_ADDRESS PHYS_SDRAM_1 | |
97 | |
98 /* | |
99 * Size of malloc() pool | |
100 */ | |
101 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | |
102 | |
103 /* size in bytes reserved for initial data */ | |
104 #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
105 | |
106 /* | |
107 * Stack space needed = | |
108 * Stack + Global Data + 3 words abort stack | |
109 * This is checked by linker script to define stack section | |
110 */ | |
111 #define CONFIG_SYS_MAX_STACK_SPACE (CONFIG_STACKSIZE + \ | |
112 CONFIG_SYS_GBL_DATA_SIZE + 12) | |
113 | |
114 /* | |
115 * Serial port Configuration | |
116 */ | |
117 #undef CONFIG_SILENT_CONSOLE | |
118 #define CFG_QC_SERIAL | |
119 #define CONFIG_CONS_INDEX 0 | |
120 #define CONFIG_BAUDRATE 115200 | |
121 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
122 | |
123 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT | |
124 | |
125 #define CONFIG_BOOTDELAY 0 | |
126 #define CONFIG_BOOTARGS "root=/dev/mmcblk0p3 rootwait noresume n
oswap ro console=ttyMSM2,115200" | |
127 #define CONFIG_BOOTCOMMAND "if mmcinfo 0; then ext2load mmc 0:3 0x2
0007fc0 boot/vmlinux.uimg; bootm 0x20007fc0; fi;" | |
128 | |
129 /* | |
130 * Miscellaneous configurable options | |
131 */ | |
132 #define CONFIG_SYS_NO_FLASH | |
133 #define CONFIG_SYS_LONGHELP | |
134 #define CONFIG_SYS_HUSH_PARSER | |
135 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
136 #define CONFIG_SYS_PROMPT "ChromeOS> " | |
137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
138 /* Print Buffer Size */ | |
139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
140 #define CONFIG_SYS_MAXARGS 16 /* max number of command args
*/ | |
141 #define CONFIG_SYS_BARGSIZE 2048 /* Boot Argument Buffer Size */ | |
142 | |
143 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x7FC0) /* default load
address in EBI1 SDRAM */ | |
144 | |
145 /*----------------------------------------------------------------------- | |
146 * Stack sizes | |
147 * | |
148 * The stack sizes are set up in start.S using the settings below | |
149 */ | |
150 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
151 #ifdef CONFIG_USE_IRQ | |
152 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
153 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
154 #endif | |
155 | |
156 /* | |
157 * SDRAM is split into 2 regions | |
158 * to accomodate ADSP as a memory hole. | |
159 */ | |
160 #define CONFIG_NR_DRAM_BANKS 2 | |
161 #define PHYS_SDRAM_1 0x20000000 /* EBI1 start */ | |
162 #define PHYS_SDRAM_1_SIZE 0x0E000000 /* 256 - 32(adsp) = 224MB (0
x0E000000)*/ | |
163 #define PHYS_SDRAM_2 0x30000000 /* EBI1, AFTER ADSP */ | |
164 #define PHYS_SDRAM_2_SIZE 0x30000000 /* For 1024MB on new memory
map */ | |
165 | |
166 /* | |
167 * Use the serial console. | |
168 */ | |
169 #define CONFIG_SERIAL_CONSOLE | |
170 | |
171 /* Console setup */ | |
172 #if defined(CONFIG_SERIAL_CONSOLE) | |
173 #define CONFIG_STDOUT "serial" | |
174 #define CONFIG_STDERR "serial" | |
175 #define CONFIG_STDIN "serial" | |
176 #else | |
177 #define CONFIG_ARM_DCC | |
178 #define CONFIG_ARM_DCC_MULTI | |
179 #define CONFIG_CPU_V7 | |
180 | |
181 #define CONFIG_STDOUT "dcc" | |
182 #define CONFIG_STDERR "dcc" | |
183 #define CONFIG_STDIN "dcc" | |
184 #endif | |
185 | |
186 #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
187 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
188 | |
189 /*----------------------------------------------------------------------- | |
190 * Shared Memory Location - | |
191 */ | |
192 #define SMEM_START 0x00100000 | |
193 #define SMEM_SIZE 0x00100000 | |
194 | |
195 /*----------------------------------------------------------------------- | |
196 * Physical Memory Map - | |
197 * U-Boot code, data, stack, etc. reside in SMI SDRAM 0x00000000-0x000FFFFF. | |
198 * There are similar parameters in the u-boot.lds linker script which also | |
199 * need to be updated. | |
200 */ | |
201 #define UBOOT_SDRAM_BASE 0x00000000 /* SMI */ | |
202 #define UBOOT_SDRAM_SIZE 0x00100000 | |
203 | |
204 /* Memory Test */ | |
205 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
206 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
207 | |
208 /* Environment */ | |
209 #define CONFIG_ENV_IS_NOWHERE | |
210 #define CONFIG_ENV_SIZE 0x2000 | |
211 | |
212 /* Boot parameter address - offset of 0x100 from base of first sdram region */ | |
213 #define CFG_QC_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
214 | |
215 /*----------------------------------------------------------------------- | |
216 * The qc_serial driver uses the register names below. Set UART_BASE | |
217 * for the desired UART. | |
218 */ | |
219 #define UART_BASE UART3_BASE | |
220 | |
221 #define CONFIG_GENERIC_MMC | |
222 #define CONFIG_QSD_SDCC | |
223 | |
224 | |
225 #ifndef CONFIG_GENERIC_MMC | |
226 /* This section regarding legacy mmc will be removed once the new | |
227 * mmc framework has been verified/tested sufficiently. If there are | |
228 * any major issues, you could go back to the legacy mmc by undefining | |
229 * the generic mmc code. | |
230 */ | |
231 | |
232 /*----------------------------------------------------------------------- | |
233 * Choose the SD controller to use. SDC1, 2, 3, or 4. | |
234 */ | |
235 #define SDC_INSTANCE 1 | |
236 #define USE_DM | |
237 #define USE_HIGH_SPEED_MODE | |
238 #define USE_4_BIT_BUS_MODE | |
239 #define CONFIG_SYS_MMC_BASE 0xF0000000 // not used, but defined t
o prevent compile error | |
240 #define PROC_COMM_VREG_SDC PM_VREG_GP6_ID | |
241 #endif | |
242 | |
243 /*----------------------------------------------------------------------- | |
244 * NAND configuration | |
245 */ | |
246 #define CONFIG_USE_ACCELERATED_PAGE_READ | |
247 | |
248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
249 #define CONFIG_SYS_NAND_BASE 0xF0000000 // not used, but defined to prev
ent compile error | |
250 | |
251 // NAND device specific register values for the NAND controller | |
252 // These values are for the Samsung MFG=0xEC DEV=0xAA device (x8, 1.65~1.95V, 2K
page) | |
253 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for page r/w | |
254 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_VAL 0xAAD400C0 | |
255 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_VAL 0x0004745C | |
256 | |
257 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for READ ID com
mand | |
258 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_RD_ID_VAL 0xA2D40000; | |
259 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_RD_ID_VAL 0x0005019C; | |
260 | |
261 //Decide whether to use proc comm to communicate with modem | |
262 //This will eventually go away. | |
263 #define USE_PROC_COMM | |
264 #define PROC_COMM_MPP_FOR_USB_VBUS PM_MPP_16 | |
265 #undef USE_PROC_COMM_USB_PHY_RESET /* proc_comm cmd to reset phy not working | |
266 rt now, but eventually it will*/ | |
267 | |
268 #endif /* __CONFIGS_CHROMEOS_ST1Q_COMMON_H */ | |
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