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| 1 /* | |
| 2 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. | |
| 3 * | |
| 4 * (C) Copyright 2002-2005 | |
| 5 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
| 6 * (C) Copyright 2002 | |
| 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 8 * Marius Groeger <mgroeger@sysgo.de> | |
| 9 * Gary Jennejohn <gj@denx.de> | |
| 10 * | |
| 11 * Configuation settings for the st1q board, based on the Qualcomm | |
| 12 * QSD8x50 surf board. | |
| 13 * | |
| 14 * See file CREDITS for list of people who contributed to this | |
| 15 * project. | |
| 16 * | |
| 17 * This program is free software; you can redistribute it and/or | |
| 18 * modify it under the terms of the GNU General Public License as | |
| 19 * published by the Free Software Foundation; either version 2 of | |
| 20 * the License, or (at your option) any later version. | |
| 21 * | |
| 22 * This program is distributed in the hope that it will be useful, | |
| 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 25 * GNU General Public License for more details. | |
| 26 * | |
| 27 * You should have received a copy of the GNU General Public License | |
| 28 * along with this program; if not, write to the Free Software | |
| 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 30 * MA 02111-1307 USA | |
| 31 */ | |
| 32 | |
| 33 #ifndef __CONFIGS_CHROMEOS_ST15_COMMON_H | |
| 34 #define __CONFIGS_CHROMEOS_ST15_COMMON_H | |
| 35 | |
| 36 #define CPU_IS_QSD8x50A | |
| 37 | |
| 38 #include <asm/arch/QSD8x50A_reg.h> | |
| 39 #include <asm-armv7Scorpion/armv7Scorpion.h> | |
| 40 #include <config.h> | |
| 41 | |
| 42 #define CONFIG_CHROMEOS_HWID "ARM ST15 TEST 7712" | |
| 43 | |
| 44 #define IO_READ32(addr) (*((volatile unsigned int *) (addr))) | |
| 45 #define IO_WRITE32(addr, val) (*((volatile unsigned int *) (addr)) = ((unsigned
int) (val))) | |
| 46 #define IO_READ16(addr) (*((volatile unsigned short *) (addr))) | |
| 47 #define IO_WRITE16(addr, val) (*((volatile unsigned short *) (addr)) = ((unsign
ed short) (val))) | |
| 48 #define IO_READ8(addr) (*((volatile char *) (addr))) | |
| 49 #define IO_WRITE8(addr, val) (*((volatile unsigned char *) (addr)) = ((unsigne
d char) (val))) | |
| 50 | |
| 51 /* | |
| 52 * High Level Configuration Options | |
| 53 * (easy to change) | |
| 54 */ | |
| 55 | |
| 56 #define CONFIG_STACK_BASE | |
| 57 | |
| 58 #define CONFIG_ARCH_CPU_INIT | |
| 59 | |
| 60 /* | |
| 61 * Machine ID for ST1.5 | |
| 62 */ | |
| 63 #define LINUX_MACH_TYPE 2627 | |
| 64 | |
| 65 #define CONFIG_SYS_HZ (32768) /* GPT Timer frequency */ | |
| 66 #define CONFIG_TCXO_HZ 19200000 /* TCX0 frequency */ | |
| 67 | |
| 68 #undef CONFIG_SHOW_BOOT_PROGRESS | |
| 69 | |
| 70 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
| 71 #define CONFIG_SETUP_MEMORY_TAGS | |
| 72 #define CONFIG_INITRD_TAG | |
| 73 | |
| 74 /* | |
| 75 * Enable to pass framebuffer info to kernel | |
| 76 * but after implementing calc_fbsize() in lcdc.c | |
| 77 */ | |
| 78 #define CONFIG_VIDEOFLB_ATAG_NOT_SUPPORTED | |
| 79 | |
| 80 #define ATAG_CORE_FLAGS 0x00000001 | |
| 81 #define ATAG_PAGE_SIZE 0x00001000 | |
| 82 #define ATAG_CORE_RDEV 0x000000FF | |
| 83 | |
| 84 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ | |
| 85 | |
| 86 /* Warm boot related constants */ | |
| 87 #define CONFIG_WARMBOOT_TRUE 0xBAC4F00D | |
| 88 #define CONFIG_WARMBOOT_FALSE 0x15FA15E2 | |
| 89 | |
| 90 /* | |
| 91 * Address where ATAGs are stored and where bootwedge used to be. | |
| 92 * 2 words at ATAGs are overwritten by power collapse routine | |
| 93 * in the kernel to cause a jump back to the | |
| 94 * power collapse exit routine in the kernel. | |
| 95 * These are restored back to their original values | |
| 96 * after successful power collapse . | |
| 97 */ | |
| 98 #define CONFIG_WARMBOOT_POWER_COLLAPSE_EXIT_ADDRESS PHYS_SDRAM_1 | |
| 99 | |
| 100 /* | |
| 101 * Size of malloc() pool | |
| 102 */ | |
| 103 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | |
| 104 | |
| 105 /* size in bytes reserved for initial data */ | |
| 106 #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
| 107 | |
| 108 /* | |
| 109 * Stack space needed = | |
| 110 * Stack + Global Data + 3 words abort stack | |
| 111 * This is checked by linker script to define stack section | |
| 112 */ | |
| 113 #define CONFIG_SYS_MAX_STACK_SPACE (CONFIG_STACKSIZE + \ | |
| 114 CONFIG_SYS_GBL_DATA_SIZE + 12) | |
| 115 | |
| 116 /* | |
| 117 * Serial port Configuration | |
| 118 */ | |
| 119 #undef CONFIG_SILENT_CONSOLE | |
| 120 #define CFG_QC_SERIAL | |
| 121 #define CONFIG_CONS_INDEX 0 | |
| 122 #define CONFIG_BAUDRATE 115200 | |
| 123 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 124 | |
| 125 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT | |
| 126 | |
| 127 #define CONFIG_CMD_SOURCE | |
| 128 | |
| 129 #define CONFIG_BOOTDELAY 0 | |
| 130 | |
| 131 #define CONFIG_BOOTARGS "quiet root=/dev/mmcblk0p3 rootwait nore
sume noswap ro loglevel=1 pmem_kernel_ebi1_size=96M pmem_adsp_size=34200K" | |
| 132 #define CONFIG_BOOTCOMMAND \ | |
| 133 "if mmcinfo 0; then " \ | |
| 134 "if ext2load mmc 0:3 0x00000000 boot/boot_script.uimg; then "\ | |
| 135 "source 0x00000000; " \ | |
| 136 "elif ext2load mmc 0:3 0x00007fc0 boot/vmlinux.uimg; then " \ | |
| 137 "bootm 0x00007fc0; " \ | |
| 138 "fi; " \ | |
| 139 "elif mmcinfo 1; then " \ | |
| 140 "if ext2load mmc 1:3 0x00000000 boot/boot_script.uimg; then "\ | |
| 141 "source 0x00000000; " \ | |
| 142 "elif ext2load mmc 1:3 0x00007fc0 boot/vmlinux.uimg; then " \ | |
| 143 "bootm 0x00007fc0; " \ | |
| 144 "fi; " \ | |
| 145 "fi;" | |
| 146 | |
| 147 /* | |
| 148 * Miscellaneous configurable options | |
| 149 */ | |
| 150 #define CONFIG_SYS_NO_FLASH | |
| 151 #define CONFIG_SYS_LONGHELP | |
| 152 #define CONFIG_SYS_HUSH_PARSER | |
| 153 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 154 #define CONFIG_SYS_PROMPT "ChromeOS> " | |
| 155 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 156 /* Print Buffer Size */ | |
| 157 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 158 #define CONFIG_SYS_MAXARGS 16 /* max number of command args
*/ | |
| 159 #define CONFIG_SYS_BARGSIZE 2048 /* Boot Argument Buffer Size */ | |
| 160 | |
| 161 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x7FC0) /* default load
address in EBI1 SDRAM */ | |
| 162 | |
| 163 /*----------------------------------------------------------------------- | |
| 164 * Stack sizes | |
| 165 * | |
| 166 * The stack sizes are set up in start.S using the settings below | |
| 167 */ | |
| 168 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
| 169 #ifdef CONFIG_USE_IRQ | |
| 170 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
| 171 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
| 172 #endif | |
| 173 | |
| 174 /* | |
| 175 * SDRAM is split into 2 regions to accommodate ADSP as a memory hole. | |
| 176 * Memory available for kernel: 224 + 768 = 992MB. | |
| 177 */ | |
| 178 #define CONFIG_NR_DRAM_BANKS 2 | |
| 179 #define PHYS_SDRAM_1 0x00000000 /* EBI1 start */ | |
| 180 #define PHYS_SDRAM_1_SIZE 0x0E000000 /* 256 - 32(adsp) = 224MB (0
x0E000000)*/ | |
| 181 #define PHYS_SDRAM_2 0x10000000 /* EBI1, AFTER ADSP */ | |
| 182 #define PHYS_SDRAM_2_SIZE 0x30000000 /* 768MB */ | |
| 183 | |
| 184 #define CONFIG_ARM_DCC | |
| 185 #define CONFIG_ARM_DCC_MULTI | |
| 186 #define CONFIG_CPU_V7 | |
| 187 | |
| 188 /* Console setup */ | |
| 189 #if defined(CONFIG_SERIAL_CONSOLE) | |
| 190 #define CONFIG_STDOUT "serial" | |
| 191 #define CONFIG_STDERR "serial" | |
| 192 #define CONFIG_STDIN "serial" | |
| 193 #elif defined(CONFIG_DCC_CONSOLE) | |
| 194 #define CONFIG_STDOUT "dcc" | |
| 195 #define CONFIG_STDERR "dcc" | |
| 196 #define CONFIG_STDIN "dcc" | |
| 197 #else /* default */ | |
| 198 #define CONFIG_STDOUT "lcd" | |
| 199 #define CONFIG_STDERR "lcd" | |
| 200 #define CONFIG_STDIN "dcc" | |
| 201 #endif | |
| 202 | |
| 203 #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 204 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
| 205 | |
| 206 /*----------------------------------------------------------------------- | |
| 207 * Shared Memory Location - | |
| 208 */ | |
| 209 #define SMEM_START 0xE0100000 | |
| 210 #define SMEM_SIZE 0x00100000 | |
| 211 | |
| 212 /*----------------------------------------------------------------------- | |
| 213 * Physical Memory Map - | |
| 214 * U-Boot code, data, stack, etc. reside in SMI SDRAM 0x00000000-0x000FFFFF. | |
| 215 * There are similar parameters in the u-boot.lds linker script which also | |
| 216 * need to be updated. | |
| 217 */ | |
| 218 #define UBOOT_SDRAM_BASE 0xE0000000 /* SMI */ | |
| 219 #define UBOOT_SDRAM_SIZE 0x00100000 | |
| 220 | |
| 221 /* Memory Test */ | |
| 222 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
| 223 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
| 224 | |
| 225 /* Environment */ | |
| 226 #define CONFIG_ENV_IS_NOWHERE | |
| 227 #define CONFIG_ENV_SIZE 0x2000 | |
| 228 | |
| 229 /* Boot parameter address - offset of 0x100 from base of first sdram region */ | |
| 230 #define CFG_QC_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
| 231 | |
| 232 /*----------------------------------------------------------------------- | |
| 233 * The qc_serial driver uses the register names below. Set UART_BASE | |
| 234 * for the desired UART. | |
| 235 */ | |
| 236 #define UART_BASE UART3_BASE | |
| 237 | |
| 238 /* MMC interface */ | |
| 239 #define CONFIG_GENERIC_MMC | |
| 240 #define CONFIG_GENERIC_MMC_MULTI_BLOCK_READ | |
| 241 #define CONFIG_QSD_SDCC | |
| 242 | |
| 243 | |
| 244 #ifndef CONFIG_GENERIC_MMC | |
| 245 /* This section regarding legacy mmc will be removed once the new | |
| 246 * mmc framework has been verified/tested sufficiently. If there are | |
| 247 * any major issues, you could go back to the legacy mmc by undefining | |
| 248 * the generic mmc code. | |
| 249 */ | |
| 250 | |
| 251 /*----------------------------------------------------------------------- | |
| 252 * Choose the SD controller to use. SDC1, 2, 3, or 4. | |
| 253 */ | |
| 254 #define SDC_INSTANCE 1 | |
| 255 #define USE_DM | |
| 256 #define USE_HIGH_SPEED_MODE | |
| 257 #define USE_4_BIT_BUS_MODE | |
| 258 #define CONFIG_SYS_MMC_BASE 0xF0000000 // not used, but defined t
o prevent compile error | |
| 259 #define PROC_COMM_VREG_SDC PM_VREG_WLAN_ID | |
| 260 #endif | |
| 261 | |
| 262 /*----------------------------------------------------------------------- | |
| 263 * NAND configuration | |
| 264 */ | |
| 265 #define CONFIG_USE_ACCELERATED_PAGE_READ | |
| 266 | |
| 267 #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 268 #define CONFIG_SYS_NAND_BASE 0xF0000000 // not used, but defined to prev
ent compile error | |
| 269 | |
| 270 // NAND device specific register values for the NAND controller | |
| 271 // These values are for the Samsung MFG=0xEC DEV=0xAA device (x8, 1.65~1.95V, 2K
page) | |
| 272 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for page r/w | |
| 273 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_VAL 0xAAD400C0 | |
| 274 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_VAL 0x0004745C | |
| 275 | |
| 276 // NAND_DEVn_CFG0 and 1 registers. These parameters are are used for READ ID com
mand | |
| 277 #define CONFIG_QC_NAND_NAND_DEVn_CFG0_RD_ID_VAL 0xA2D40000; | |
| 278 #define CONFIG_QC_NAND_NAND_DEVn_CFG1_RD_ID_VAL 0x0005019C; | |
| 279 | |
| 280 //Decide whether to use proc comm to communicate with modem | |
| 281 //This will eventually go away. | |
| 282 #define USE_PROC_COMM | |
| 283 #define PROC_COMM_MPP_FOR_USB_VBUS PM_MPP_16 | |
| 284 #undef USE_PROC_COMM_USB_PHY_RESET /* proc_comm cmd to reset phy not working | |
| 285 rt now, but eventually it will*/ | |
| 286 | |
| 287 #endif /* __CONFIGS_CHROMEOS_ST15_COMMON_H */ | |
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Chromium Code Reviews
Issue 6731090:
Remove ChromeOS specific configs from the U-Boot repository. (Closed)
Base URL: ssh://gitrw.chromium.org:9222/u-boot-next.git@chromeos-v2010.09