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1 /* | |
2 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. | |
3 * | |
4 * (C) Copyright 2002-2005 | |
5 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
6 * (C) Copyright 2002 | |
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 * Marius Groeger <mgroeger@sysgo.de> | |
9 * Gary Jennejohn <gj@denx.de> | |
10 * | |
11 * Configuation settings for the QRDC board, based on the Qualcomm | |
12 * MSM8x60 surf board. | |
13 * | |
14 * See file CREDITS for list of people who contributed to this | |
15 * project. | |
16 * | |
17 * This program is free software; you can redistribute it and/or | |
18 * modify it under the terms of the GNU General Public License as | |
19 * published by the Free Software Foundation; either version 2 of | |
20 * the License, or (at your option) any later version. | |
21 * | |
22 * This program is distributed in the hope that it will be useful, | |
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 * GNU General Public License for more details. | |
26 * | |
27 * You should have received a copy of the GNU General Public License | |
28 * along with this program; if not, write to the Free Software | |
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 * MA 02111-1307 USA | |
31 */ | |
32 | |
33 #ifndef __CONFIGS_CHROMEOS_QRDC_COMMON_H | |
34 #define __CONFIGS_CHROMEOS_QRDC_COMMON_H | |
35 | |
36 #define CPU_IS_MSM8x60 | |
37 | |
38 #include <asm/arch/MSM8x60_reg.h> | |
39 #include <asm-armv7Scorpion/armv7Scorpion.h> | |
40 #include <config.h> | |
41 | |
42 #define CONFIG_CHROMEOS_HWID "ARM QRDC TEST 0689" | |
43 | |
44 #define IO_READ32(addr) (*((volatile unsigned int *) (addr))) | |
45 #define IO_WRITE32(addr, val) (*((volatile unsigned int *) (addr)) = ((unsigned
int) (val))) | |
46 #define IO_READ16(addr) (*((volatile unsigned short *) (addr))) | |
47 #define IO_WRITE16(addr, val) (*((volatile unsigned short *) (addr)) = ((unsign
ed short) (val))) | |
48 #define IO_READ8(addr) (*((volatile char *) (addr))) | |
49 #define IO_WRITE8(addr, val) (*((volatile unsigned char *) (addr)) = ((unsigne
d char) (val))) | |
50 | |
51 /* | |
52 * High Level Configuration Options | |
53 * (easy to change) | |
54 */ | |
55 | |
56 #define CONFIG_STACK_BASE | |
57 | |
58 | |
59 /* | |
60 * Undefine Machine ID if defined in common board files. | |
61 * Redefine the Machine ID for QRDC Board | |
62 */ | |
63 #ifdef LINUX_MACH_TYPE | |
64 #undef LINUX_MACH_TYPE | |
65 #endif /* LINUX_MACH_TYPE */ | |
66 | |
67 #define LINUX_MACH_TYPE (3060) | |
68 | |
69 #define CONFIG_SYS_HZ (32768) /* GPT Timer frequency */ | |
70 #define CONFIG_TCXO_HZ 19200000 /* TCX0 frequency */ | |
71 | |
72 #undef CONFIG_SHOW_BOOT_PROGRESS | |
73 | |
74 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
75 #define CONFIG_SETUP_MEMORY_TAGS | |
76 //#define CONFIG_INITRD_TAG | |
77 | |
78 /* | |
79 * Enable to pass framebuffer info to kernel | |
80 * but after implementing calc_fbsize() in lcdc.c | |
81 */ | |
82 #define CONFIG_VIDEOFLB_ATAG_NOT_SUPPORTED | |
83 | |
84 #define ATAG_CORE_FLAGS 0x00000004 | |
85 #define ATAG_PAGE_SIZE 0x00001000 | |
86 #define ATAG_CORE_RDEV 0x000000FF | |
87 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ | |
88 | |
89 /* Warm boot related constants */ | |
90 #define CONFIG_WARMBOOT_TRUE 0xBAC4F00D | |
91 #define CONFIG_WARMBOOT_FALSE 0x15FA15E2 | |
92 | |
93 /* | |
94 * Address where ATAGs are stored and where bootwedge used to be. | |
95 * 2 words at ATAGs are overwritten by power collapse routine | |
96 * in the kernel to cause a jump back to the | |
97 * power collapse exit routine in the kernel. | |
98 * These are restored back to their original values | |
99 * after successful power collapse . | |
100 */ | |
101 #define CONFIG_WARMBOOT_POWER_COLLAPSE_EXIT_ADDRESS PHYS_SDRAM_1 | |
102 | |
103 /* | |
104 * Size of malloc() pool | |
105 */ | |
106 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | |
107 | |
108 /* size in bytes reserved for initial data */ | |
109 #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
110 | |
111 /* | |
112 * Stack space needed = | |
113 * Stack + Global Data + 3 words abort stack | |
114 * This is checked by linker script to define stack section | |
115 */ | |
116 #define CONFIG_SYS_MAX_STACK_SPACE (CONFIG_STACKSIZE + \ | |
117 CONFIG_SYS_GBL_DATA_SIZE + 12) | |
118 | |
119 /* | |
120 * Serial port Configuration | |
121 */ | |
122 #undef CONFIG_SILENT_CONSOLE | |
123 #define CFG_QC_SERIAL | |
124 #define CONFIG_CONS_INDEX 0 | |
125 #define CONFIG_BAUDRATE 115200 | |
126 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
127 | |
128 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT | |
129 | |
130 #define CONFIG_CMD_SOURCE | |
131 | |
132 #define CONFIG_BOOTDELAY 0 | |
133 | |
134 #define CONFIG_BOOTARGS "console=tty0 root=/dev/mmcblk1p3 rootwait init=/sbin/in
it pmem_kernel_ebi1_size=32M" | |
135 | |
136 #define CONFIG_BOOTCOMMAND \ | |
137 "if mmcinfo 1; then " \ | |
138 "if ext2load mmc 1:3 0x40200000 boot/boot_script.uimg; then "\ | |
139 "source 0x40200000; " \ | |
140 "elif ext2load mmc 1:3 0x40207fc0 boot/vmlinux.uimg; then " \ | |
141 "bootm 0x40207fc0; " \ | |
142 "fi; " \ | |
143 "elif mmcinfo 0; then " \ | |
144 "if ext2load mmc 0:3 0x40200000 boot/boot_script.uimg; then "\ | |
145 "source 0x40200000; " \ | |
146 "elif ext2load mmc 0:3 0x40207fc0 boot/vmlinux.uimg; then " \ | |
147 "bootm 0x40207fc0; " \ | |
148 "fi; " \ | |
149 "fi;" | |
150 | |
151 /* | |
152 * Miscellaneous configurable options | |
153 */ | |
154 #define CONFIG_SYS_NO_FLASH | |
155 #define CONFIG_SYS_LONGHELP | |
156 #define CONFIG_SYS_HUSH_PARSER | |
157 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
158 #define CONFIG_SYS_PROMPT "ChromeOS> " | |
159 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
160 /* Print Buffer Size */ | |
161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
162 #define CONFIG_SYS_MAXARGS 16 /* max number of command args
*/ | |
163 #define CONFIG_SYS_BARGSIZE 2048 /* Boot Argument Buffer Size */ | |
164 | |
165 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x7FC0) /* default load
address in EBI1 SDRAM */ | |
166 | |
167 /*----------------------------------------------------------------------- | |
168 * Stack sizes | |
169 * | |
170 * The stack sizes are set up in start.S using the settings below | |
171 */ | |
172 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
173 #ifdef CONFIG_USE_IRQ | |
174 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
175 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
176 #endif | |
177 | |
178 /* | |
179 * SDRAM: Memory available for kernel: 510MB. | |
180 */ | |
181 #define CONFIG_NR_DRAM_BANKS 1 | |
182 #define PHYS_SDRAM_1 0x40200000 | |
183 #define PHYS_SDRAM_1_SIZE 0x1FE00000 /* 510MB */ | |
184 | |
185 #define CONFIG_ARM_DCC | |
186 #define CONFIG_ARM_DCC_MULTI | |
187 #define CONFIG_CPU_V7 | |
188 #define CONFIG_SERIAL_CONSOLE | |
189 //#define CONFIG_DCC_CONSOLE | |
190 | |
191 /* Console setup */ | |
192 #if defined(CONFIG_SERIAL_CONSOLE) | |
193 #define CONFIG_STDOUT "serial" | |
194 #define CONFIG_STDERR "serial" | |
195 #define CONFIG_STDIN "serial" | |
196 #elif defined(CONFIG_DCC_CONSOLE) | |
197 #define CONFIG_STDOUT "dcc" | |
198 #define CONFIG_STDERR "dcc" | |
199 #define CONFIG_STDIN "dcc" | |
200 #else /* default */ | |
201 #define CONFIG_STDOUT "lcd" | |
202 #define CONFIG_STDERR "lcd" | |
203 #define CONFIG_STDIN "dcc" | |
204 #endif | |
205 | |
206 #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
207 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
208 | |
209 /*----------------------------------------------------------------------- | |
210 * Shared Memory Location - | |
211 */ | |
212 #define SMEM_START 0xE0100000 | |
213 #define SMEM_SIZE 0x00100000 | |
214 | |
215 /*----------------------------------------------------------------------- | |
216 * Physical Memory Map - | |
217 * U-Boot code, data, stack, etc. reside in external RAM. | |
218 */ | |
219 #define UBOOT_SDRAM_BASE 0x40100000 /* external ram */ | |
220 #define UBOOT_SDRAM_SIZE 0x00100000 | |
221 | |
222 /* Memory Test */ | |
223 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
224 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
225 | |
226 /* Environment */ | |
227 #define CONFIG_ENV_IS_NOWHERE | |
228 #define CONFIG_ENV_SIZE 0x2000 | |
229 | |
230 /* Boot parameter address - offset of 0x100 from base of first sdram region */ | |
231 #define CFG_QC_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
232 | |
233 /*----------------------------------------------------------------------- | |
234 * The qc_serial driver uses the register names below. Set UART_BASE | |
235 * for the desired UART. | |
236 */ | |
237 #define UART_BASE UART3_BASE | |
238 | |
239 /* MMC interface */ | |
240 #define CONFIG_GENERIC_MMC | |
241 #define CONFIG_GENERIC_MMC_MULTI_BLOCK_READ | |
242 #define CONFIG_QSD_SDCC | |
243 | |
244 /* Ethernet support */ | |
245 #define CONFIG_CMD_NET | |
246 #define CONFIG_NET_MULTI | |
247 #define CONFIG_CMD_DHCP | |
248 #define CONFIG_CMD_PING | |
249 | |
250 #define CONFIG_SMC911X | |
251 #define CONFIG_SMC911X_16_BIT | |
252 #define CONFIG_SMC911X_BASE 0x1B800000 | |
253 | |
254 #endif /* __CONFIGS_CHROMEOS_QRDC_COMMON_H */ | |
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