Add Tegra2 SPI controller.

tegra2_spi.c

Index: tegra2_spi.c
diff --git a/tegra2_spi.c b/tegra2_spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..72d1813222e65ae452a263868837aefe9a160358
--- /dev/null
+++ b/tegra2_spi.c
@@ -0,0 +1,429 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2010 NVIDIA Corporation
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#if defined(__arm__)
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "flash.h"
+#include "programmer.h"
+#include "tegra2_spi.h"
+
+static void *gpio_base, *clkrst_base, *apbmisc_base, *spi_base;
+
+#define SPI_TIMEOUT 10000  /* 100ms = 10000 * 10us */
+
+/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
+#define UART_DISABLE_PORT 8
+#define UART_DISABLE_BIT 3
+
+/* Config port:bit as GPIO, not SFPIO (default) */
+static void __set_config(unsigned port, unsigned bit, int type)
+{
+	u32 u;
+
+	msg_pdbg("%s: port = %d, bit = %d, %s\n", __FUNCTION__,
+	         port, bit, type ? "GPIO" : "SFPIO");
+
+	u = mmio_readl(GPIO_CNF(port));
+	if (type)  /* GPIO */
+		u |= 1 << bit;
+	else
+		u &= ~(1 << bit);
+	mmio_writel(u, GPIO_CNF(port));
+}
+
+/* Config GPIO port:bit as input or output (OE) */
+static void __set_direction(unsigned port, unsigned bit, int output)
+{
+	u32 u;
+
+	msg_pdbg("%s: port = %d, bit = %d, %s\n", __FUNCTION__,
+	         port, bit, output ? "OUT" : "IN");
+
+	u = mmio_readl(GPIO_OE(port));
+	if (output)
+		u |= 1 << bit;
+	else
+		u &= ~(1 << bit);
+	mmio_writel(u, GPIO_OE(port));
+}
+
+/* set GPIO OUT port:bit as 0 or 1 */
+static void __set_level(unsigned port, unsigned bit, int high)
+{
+	u32 u;
+
+	msg_pdbg("%s: port = %d, bit %d == %d\n", __FUNCTION__,
+	         port, bit, high);
+
+	u = mmio_readl(GPIO_OUT(port));
+	if (high)
+		u |= 1 << bit;
+	else
+		u &= ~(1 << bit);
+	mmio_writel(u, GPIO_OUT(port));
+}
+
+
+/* set GPIO port:bit as an output, with polarity 'value' */
+static int tg2_gpio_direction_output(unsigned port, unsigned bit, int value)
+{
+	msg_pdbg("%s: port = %d, bit = %d, value = %d\n",
+	         __FUNCTION__, port, bit, value);
+
+	/* Configure as a GPIO */
+	__set_config(port, bit, 1);
+
+	/* Configure GPIO output value. */
+	__set_level(port, bit, value);
+
+	/* Configure GPIO direction as output. */
+	__set_direction(port, bit, 1);
+
+	return 0;
+}
+
+
+/* SPI controller register related init code. */
+static void spi_init(void)
+{
+	uint32_t *spi_cmd = (uint32_t *)spi_base;
+	uint32_t *spi_sts = (uint32_t *)(spi_base + 0x04);
+	uint32_t *clkrst_enb;
+	u32 val;
+
+	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+	tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 0);
+
+	/*
+	 * SPI reset/clocks init - reset SPI, set clocks, release from reset
+	 */
+	val =  mmio_readl(clkrst_base + 0x08);
+	mmio_writel((val | 0x800), (clkrst_base + 0x08));
+	msg_pdbg("spi_init: ClkRst = %08x\n", val);
+
+	val =  mmio_readl(clkrst_base + 0x14);
+	mmio_writel((val | 0x800), (clkrst_base + 0x14));
+	msg_pdbg("spi_init: ClkEnable = %08x\n", val);
+
+	/* Change default SPI clock from 12MHz to 6MHz, same as BootROM */
+	val =  mmio_readl(clkrst_base + 0x114);
+	mmio_writel((val | 0x2), (clkrst_base + 0x114));
+	msg_pdbg("spi_init: ClkSrc = %08x\n", val);
+
+	val =  mmio_readl(clkrst_base + 0x08);
+	mmio_writel((val & 0xFFFFF7FF), (clkrst_base + 0x08));
+	msg_pdbg("spi_init: ClkRst final = %08x\n", val);
+
+	/* Clear stale status here */
+	mmio_writel(SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH |
+	            SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF, spi_sts);
+	msg_pdbg("%s: STATUS = %08x\n", __FUNCTION__, mmio_readl(spi_sts));
+
+	/*
+	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+	 */
+	mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_SOFT, spi_cmd);
+	msg_pdbg("%s: COMMAND = %08x\n", __FUNCTION__, mmio_readl(spi_cmd));
+
+	/*
+	 * SPI pins on Tegra2 are muxed - change pinmux last due to UART issue
+	 */
+	val = mmio_readl(apbmisc_base + 0x88);
+	val |= 0xC0000000;
+	mmio_writel(val, (apbmisc_base + 0x88));
+	msg_pdbg("spi_init: PinMuxRegC = %08x\n", val);
+
+	val = mmio_readl(apbmisc_base + 0x20);
+	val &= 0xFFFFFFFE;
+	mmio_writel(val, (apbmisc_base + 0x20));
+	msg_pdbg("spi_init: TriStateReg = %08x\n", val);
+
+	/* delay 100ms so that all chars in buffer (1KB) can be flushed. */
+	programmer_delay(100000);

[Micah C, 2011/03/28 02:08:22]

This is a big delay.  Is there any other signal that can be used to indicate the
transfer has been finished which might sometimes come sooner than 100ms?

[Louis, 2011/03/30 10:15:39]

I don't know a signal for this. Actually, this is only called once, and should
not a big deal.

On 2011/03/28 02:08:22, Micah C wrote:

+
+	/*
+	 * We need to dynamically change the pinmux, shared w/UART RXD/CTS!
+	 */
+	val = mmio_readl(apbmisc_base + 0x84);
+	val |= 0x0000000C;  /* 3 = SFLASH */
+	mmio_writel(val, (apbmisc_base + 0x84));
+	msg_pdbg("%s: PinMuxRegB = %08x\n", __FUNCTION__, val);
+
+	/* On Seaboard, MOSI/MISO are shared w/UART.
+	 * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
+	 * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
+	 */
+	msg_pdbg("%s: DISABLING UART!\n", __FUNCTION__);
+	tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 1);
+
+	/* wait for UART Tx FIFO flushed. */
+	programmer_delay(2000);

[Micah C, 2011/03/28 02:08:22]

Is there some status register that can detect UART Tx FIFO empty which is more
reliable than a CPU delay?

[Louis, 2011/03/30 10:15:39]

This is not necessary because nothing will be send out when UART is disbled.
Removed.
On 2011/03/28 02:08:22, Micah C wrote:

+}
+
+/* SPI controller register related shutdown code. */
+static void spi_shutdown(void) {
+	u32 val;
+
+	/*
+	 * Looks like we may also need to dynamically change the pinmux,

[Micah C, 2011/03/28 02:08:22]

It might be a good idea to create functions like "save_pinmux_state()" and
"restore_pinmux_state()" to use from spi_init() and spi_shutdown().  If there
are many different boards in the world with Tegra2 CPUs, they might have
different pinmux settings than Seaboard, so hardcoding the constant settings in
spi_shutdown may be brittle.

[Louis, 2011/03/30 10:15:39]

Done. Call register_shutdown() to restore all changed register in the end.

+	 *  shared w/UART RXD/CTS!
+	 */
+	val = mmio_readl(apbmisc_base + 0x84);
+	val &= 0xFFFFFFF3;  /* 0 = UART */
+	mmio_writel(val, (apbmisc_base + 0x84));
+	msg_pdbg("%s: PinMuxRegB = %08x\n", __FUNCTION__, val);
+
+	/* On Seaboard, MOSI/MISO are shared w/UART.
+	 * GPIO I3 (UART_DISABLE) was used to tristate UART in cs_activate.
+	 * Enable UART here by setting that GPIO to 0 so we can do U-Boot comms.
+	 */
+	tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 0);
+	msg_pdbg("%s: ENABLED UART!\n", __FUNCTION__);
+}
+
+
+static void spi_cs_activate(void)
+{
+	uint32_t *spi_cmd = (uint32_t *)spi_base;
+
+	/*
+	 * CS is negated on Tegra, so drive a 1 to get a 0
+	 */
+	mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_VAL, spi_cmd);
+	msg_pdbg("%s: CS driven %s\n", __FUNCTION__,
+	         (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH");
+}
+
+static void spi_cs_deactivate(void)
+{
+	uint32_t *spi_cmd = (uint32_t *)spi_base;
+
+
+	/*
+	 * CS is negated on Tegra, so drive a 0 to get a 1
+	*/
+	mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_CS_VAL, spi_cmd);
+	msg_pdbg("%s: CS driven %s\n", __FUNCTION__,
+	         (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH");
+}
+
+
+/* Helper function to calculate the clock cycle in this round.
+ * Also updates the byte count remaining to be used this round.
+ *
+ * For example, we want to write 6 bytes to SPI and then read 5 bytes back.
+ *
+ * +---+---+---+---+---+---+
+ * | W | W | W | W | W | W |
+ * +---+---+---+---+---+---+---+---+---+---+---+
+ *                         | R | R | R | R | R |
+ *                         +---+---+---+---+---+
+ * |<-- round 0 -->|
+ *                 |<-- round 1 -->|
+ *                                 |<-- round 2 -->|
+ *
+ * So that the continuous calling this function would get:
+ *
+ * round| RET| writecnt  readcnt  bits  to_write  to_read
+ * -----+----+---------------------------------------------
+ * INIT |    |     6        5
+ *    0 |  1 |     2        5      32       4        0
+ *    1 |  1 |     0        3      32       2        2
+ *    2 |  1 |     0        0      24       0        3
+ *    3 |  0 |     -        -       -       -        -
+ *
+ */
+int next4Bytes(uint32_t *writecnt, uint32_t *readcnt, int *num_bits,
+               uint32_t *to_write, uint32_t *to_read) {
+	assert(writecnt);
+	assert(readcnt);
+	assert(num_bits);
+	assert(to_write);
+	assert(to_read);
+
+	*to_write = min(*writecnt, 4);
+	*to_read = min(*readcnt, 4 - *to_write);
+
+	*writecnt -= *to_write;
+	*readcnt -= *to_read;
+
+	*num_bits = (*to_write + *to_read) * 8;
+
+	if (*num_bits)
+		return 1;  /* need to be called again. */
+	else
+		return 0;  /* handled write and read requests. */
+}
+
+/*
+ * Tegra2 FIFO design is ... interesting. For example, you want to Tx 2 bytes:
+ *
+ *                +---+---+
+ *    writearr[]: | 0 | 1 |
+ *                +---+---+
+ *                    \   \
+ *                     \   \
+ *                      \   \
+ *                       \   \
+ *                        \   \
+ *             31 +---+---+---+---+ 0
+ *  tmp(32-bits): | X | X | 0 | 1 |
+ *                +---+---+---+---+ LSB
+ *
+ * It is neither little or big endian. The first bit for SPI controller to
+ * transfer is the bit 15 in FIFO, neither bit 31 or bit 0, because the transfer
+ * length is 16 bits (2 bytes).
+ *
+ * Rx follows the similar rule. First bit comes at bit 0, and the whole FIFO
+ * left-shifts 1 bit for every bit comes in. Hence, after reading 3 bytes,
+ * the first coming bit will reside in bit 23.
+ */
+int tegra2_spi_send_command(unsigned int writecnt,
+                            unsigned int readcnt,
+                            const unsigned char *writearr,
+                            unsigned char *readarr)
+{
+	int retval = 0;
+	uint8_t *delayed_msg = NULL;  /* for UART is disabled. */
+	uint32_t *spi_cmd = (uint32_t *)spi_base;
+	uint32_t *spi_sts = (uint32_t *)(spi_base + 0x04);
+	uint32_t *tx_fifo = (uint32_t *)(spi_base + 0x10);
+	uint32_t *rx_fifo = (uint32_t *)(spi_base + 0x20);
+	uint32_t status;
+	uint32_t to_write, to_read;  /*  byte counts to fill FIFO. */
+	uint32_t bits;  /* bit count to tell SPI controller. */
+
+	mmio_writel(mmio_readl(spi_sts), spi_sts);
+	mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_TXEN | SPI_CMD_RXEN, spi_cmd);
+	spi_cs_activate();
+
+	while (next4Bytes(&writecnt, &readcnt, &bits, &to_write, &to_read)) {
+		int i;
+		uint32_t tmp;
+		uint32_t tm;  /* timeout counter */
+
+		/* prepare Tx FIFO */
+		for (tmp = 0, i = 0; i < to_write; ++i) {
+			tmp |= (*writearr++) << ((bits / 8 - 1 - i) * 8);
+		}
+		mmio_writel(tmp, tx_fifo);
+
+		/* Kick the SCLK running: Shift out TX FIFO, and receive RX. */
+		mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_BIT_LENGTH_MASK,
+		            spi_cmd);
+		mmio_writel(mmio_readl(spi_cmd) | (bits - 1),
+		            spi_cmd);
+		mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_GO, spi_cmd);
+
+		/* Wait for controller completes the task. */
+		for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
+			if (((status = mmio_readl(spi_sts)) &
+			    (SPI_STAT_BSY | SPI_STAT_RDY)) == SPI_STAT_RDY)
+				break;
+			programmer_delay(10);

[Micah C, 2011/03/28 02:08:22]

Is this "10" the same 10us that's multiplied into the SPI_TIMEOUT definition? 
Perhaps it deserves its own constant if it's something that's specified for the
controller interface.

[Louis, 2011/03/30 10:15:39]

Good catch. I refined this to 2us (roughly larger than 1.333 us = 1 / 6MHz * 8
bits)
On 2011/03/28 02:08:22, Micah C wrote:

+		}
+		mmio_writel(mmio_readl(spi_sts) | SPI_STAT_RDY, spi_sts);
+
+		/* Since the UART is disabled here, we delay printing the
+		 * message until spi_cs_deactivate() is called.
+		 */
+		if (tm >= SPI_TIMEOUT) {
+			static uint8_t err[256];
+			retval = -1;
+			snprintf(err, sizeof(err),
+			         "%s():%d BSY&RDY timeout, status = 0x%08x\n",
+			         __FUNCTION__, __LINE__, status);
+			delayed_msg = err;
+			break;
+		}
+
+		/* read RX FIFO */
+		tmp = mmio_readl(rx_fifo);
+		for (i = 0; i < to_read; ++i) {
+			*readarr++ = (tmp >> ((to_read - 1 - i) * 8)) & 0xFF;
+		}
+	}
+
+	mmio_writel(status = mmio_readl(spi_sts), spi_sts);
+
+	spi_cs_deactivate();
+	if (delayed_msg) {
+		msg_perr("%s\n", delayed_msg);
+	}
+
+	return retval;
+}
+
+
+int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+{
+	return spi_read_chunked(flash, buf, start, len, 256);
+}
+
+
+int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len)
+{
+	return spi_write_chunked(flash, buf, start, len, 256);
+}
+
+
+/* Map register spaces */
+int tegra2_spi_init(void)
+{
+	int error = 0;
+
+	gpio_base = physmap("GPIO", TEGRA2_GPIO_BASE, 4096);
+	clkrst_base = physmap("CLK/RST", NV_ADDRESS_MAP_PPSB_CLK_RST_BASE,
+	                      4096);
+	apbmisc_base = physmap("APB MISC", NV_ADDRESS_MAP_APB_MISC_BASE, 4096);
+	/* non-page offset */
+	spi_base = physmap("SPI", TEGRA2_SPI_BASE - 0x380, 4096) + 0x380;
+
+	if (error)
+		return 1;
+
+	flashbase = 0;  /* FIXME: to make sanity check happy. */
+	buses_supported = CHIP_BUSTYPE_SPI;
+	spi_controller = SPI_CONTROLLER_TEGRA2;
+
+	spi_init();

[Stefan Reinauer, 2011/03/25 17:22:03]

It seems spi_init() could just be rolled into this function. Having
tegra2_spi_init() and a separate spi_init() does not add to making the code
easier to understand.

[Louis, 2011/03/30 10:15:39]

Done.

+
+	return 0;
+}
+
+
+/* Unmap register spaces */
+int tegra2_spi_shutdown(void)
+{
+	spi_shutdown();

[Stefan Reinauer, 2011/03/25 17:22:03]

Same applies for tegra2_spi_shutdown() and spi_shutdown().

[Louis, 2011/03/30 10:15:39]

Done.

+
+	physunmap(gpio_base, 4096);
+	physunmap(clkrst_base, 4096);
+	physunmap(apbmisc_base, 4096);
+	physunmap(spi_base - 0x380, 4096);
+
+	return 0;
+}
+#endif