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Side by Side Diff: tegra2_spi.h

Issue 6731011: Add Tegra2 SPI controller. (Closed) Base URL: ssh://git@gitrw.chromium.org:9222/flashrom.git@master
Patch Set: refine according to code review. Created 9 years, 9 months ago
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1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 NVIDIA Corporation
5 * Copyright (C) 2011 Google Inc
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22 #ifndef __TEGRA2_SPI_H__
23 #define __TEGRA2_SPI_H__
24
25 // ***************************************************************************
26 // Hardware BARs
27
28 #define TEGRA2_GPIO_BASE 0x6000D000
29 #define TEGRA2_SPI_BASE 0x7000C380
30 #define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 0x60006000
31 #define NV_ADDRESS_MAP_APB_MISC_BASE 0x70000000
32
33 // ***************************************************************************
34 // Clock/reset controller
35 #define CLK_RST_ENB_H_0_OFFSET 0x14
36 #define CLK_RST_ENB_H_0_SPI1 (1 << 11)
37
38 // ***************************************************************************
39 // GPIO controller
40
41 #define GPIO_OFF(port) (((port / 4) * 128) + ((port % 4) * 4))
42 #define GPIO_CNF(port) (gpio_base + GPIO_OFF(port) + 0x00)
43 #define GPIO_OE(port) (gpio_base + GPIO_OFF(port) + 0x10)
44 #define GPIO_OUT(port) (gpio_base + GPIO_OFF(port) + 0x20)
45 #define GPIO_IN(port) (gpio_base + GPIO_OFF(port) + 0x30)
46 #define GPIO_INT_STA(port) (gpio_base + GPIO_OFF(port) + 0x40)
47 #define GPIO_INT_ENB(port) (gpio_base + GPIO_OFF(port) + 0x50)
48 #define GPIO_INT_LVL(port) (gpio_base + GPIO_OFF(port) + 0x60)
49 #define GPIO_INT_CLR(port) (gpio_base + GPIO_OFF(port) + 0x70)
50
51 // ***************************************************************************
52 // go away code
53
54 #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
55 #define SPI_XFER_END 0x02 /* Deassert CS after transfer */
56
Stefan Reinauer 2011/03/25 17:01:17 The whole "go away code" section is not used anymo
Louis 2011/03/30 10:15:39 Done.
57 // ***************************************************************************
58 // SPI controller
59
60 typedef struct spi_tegra {
61 uint32_t command; /* SPI_COMMAND_0 register */
62 uint32_t status; /* SPI_STATUS_0 register */
63 uint32_t rx_cmp; /* SPI_RX_CMP_0 register */
64 uint32_t dma_ctl; /* SPI_DMA_CTL_0 register */
65 uint32_t tx_fifo; /* SPI_TX_FIFO_0 register */
66 uint32_t rsvd[3]; /* offsets 0x14 to 0x1F reserved */
67 uint32_t rx_fifo; /* SPI_RX_FIFO_0 register */
68
69 } spi_tegra_t;
Stefan Reinauer 2011/03/25 17:01:17 This struct is no longer used. It should be droppe
Louis 2011/03/30 10:15:39 Done.
70
71 #define SPI_CMD_GO (1 << 30)
72 #define SPI_CMD_ACTIVE_SCLK (1 << 26)
73 #define SPI_CMD_CK_SDA (1 << 21)
74 #define SPI_CMD_ACTIVE_SDA (1 << 18)
75 #define SPI_CMD_CS_POL (1 << 16)
76 #define SPI_CMD_TXEN (1 << 15)
77 #define SPI_CMD_RXEN (1 << 14)
78 #define SPI_CMD_CS_VAL (1 << 13)
79 #define SPI_CMD_CS_SOFT (1 << 12)
80 #define SPI_CMD_CS_DELAY (1 << 9)
81 #define SPI_CMD_CS3_EN (1 << 8)
82 #define SPI_CMD_CS2_EN (1 << 7)
83 #define SPI_CMD_CS1_EN (1 << 6)
84 #define SPI_CMD_CS0_EN (1 << 5)
85 #define SPI_CMD_BIT_LENGTH (1 << 4)
86 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
87
88 #define SPI_STAT_BSY (1 << 31)
89 #define SPI_STAT_RDY (1 << 30)
90 #define SPI_STAT_RXF_FLUSH (1 << 29)
91 #define SPI_STAT_TXF_FLUSH (1 << 28)
92 #define SPI_STAT_RXF_UNR (1 << 27)
93 #define SPI_STAT_TXF_OVF (1 << 26)
94 #define SPI_STAT_RXF_EMPTY (1 << 25)
95 #define SPI_STAT_RXF_FULL (1 << 24)
96 #define SPI_STAT_TXF_EMPTY (1 << 23)
97 #define SPI_STAT_TXF_FULL (1 << 22)
98 #define SPI_STAT_SEL_TXRX_N (1 << 16)
99 #define SPI_STAT_CUR_BLKCNT (1 << 15)
100
101 #endif /* __TEGRA2_SPI_H__ */
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