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1 // Copyright 2007-2008 the V8 project authors. All rights reserved. | 1 // Copyright 2007-2008 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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254 switch (swi) { | 254 switch (swi) { |
255 case call_rt_r5: | 255 case call_rt_r5: |
256 Print("call_rt_r5"); | 256 Print("call_rt_r5"); |
257 return; | 257 return; |
258 case call_rt_r2: | 258 case call_rt_r2: |
259 Print("call_rt_r2"); | 259 Print("call_rt_r2"); |
260 return; | 260 return; |
261 case break_point: | 261 case break_point: |
262 Print("break_point"); | 262 Print("break_point"); |
263 return; | 263 return; |
| 264 case simulator_fp_add: |
| 265 Print("simulator_fp_add"); |
| 266 return; |
| 267 case simulator_fp_mul: |
| 268 Print("simulator_fp_mul"); |
| 269 return; |
| 270 case simulator_fp_sub: |
| 271 Print("simulator_fp_sub"); |
| 272 return; |
264 default: | 273 default: |
265 out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, | 274 out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
266 "%d", | 275 "%d", |
267 swi); | 276 swi); |
268 return; | 277 return; |
269 } | 278 } |
270 } | 279 } |
271 | 280 |
272 | 281 |
273 // Handle all register based formatting in this function to reduce the | 282 // Handle all register based formatting in this function to reduce the |
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882 buffer[0] = '\0'; | 891 buffer[0] = '\0'; |
883 byte* prev_pc = pc; | 892 byte* prev_pc = pc; |
884 pc += d.InstructionDecode(buffer, pc); | 893 pc += d.InstructionDecode(buffer, pc); |
885 fprintf(f, "%p %08x %s\n", | 894 fprintf(f, "%p %08x %s\n", |
886 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 895 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
887 } | 896 } |
888 } | 897 } |
889 | 898 |
890 | 899 |
891 } // namespace disasm | 900 } // namespace disasm |
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