Fix Seaboard UART corruption on SPI activity

drivers/spi/tegra2_spi.c

 /*
  * Copyright (c) 2010 NVIDIA Corporation
  * With help from the mpc8xxx SPI driver
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ skipping 137 matching lines @@
 void spi_release_bus(struct spi_slave *slave)
 {
         /* Release UART_DISABLE and set pinmux to UART4 here? */
 }
 
 void spi_cs_activate(struct spi_slave *slave)
 {
         volatile spi_tegra_t *spi = (spi_tegra_t *)TEGRA2_SPI_BASE;
         u32 val;
 
-        /*
-         * Delay here to clean up comms - spurious chars seen around SPI xfers.
-         * Fine-tune later.
-         */
-        udelay(1000);
-
+#ifdef CONFIG_SPI_CORRUPTS_UART
+        NS16550_drain(CONFIG_SPI_CORRUPTS_UART);
+#endif
         /*
          * We need to dynamically change the pinmux, shared w/UART RXD/CTS!
          */
 
         val = NV_READ32(NV_ADDRESS_MAP_APB_MISC_BASE + 0x84);
         val |= 0x0000000C;                                      /* 3 = SFLASH */
         NV_WRITE32((NV_ADDRESS_MAP_APB_MISC_BASE + 0x84), val);
         debug("spi_init: PinMuxRegB = %08x\n", val);
 
         /* On Seaboard, MOSI/MISO are shared w/UART.
@@ skipping 12 matching lines @@
         debug("spi_cs_activate: CS driven %s\n",
          (spi->command & SPI_CMD_CS_VAL) ? "LOW" : "HIGH");
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
         volatile spi_tegra_t *spi = (spi_tegra_t *) TEGRA2_SPI_BASE;
         u32 val;
 
         /*
-         * Delay here to clean up comms - spurious chars seen around SPI xfers.
-         * Fine-tune later.
-         */
-        udelay(1000);
-
-        /*
          * Looks like we may also need to dynamically change the pinmux,
          *  shared w/UART RXD/CTS!
          */
 
         val = NV_READ32(NV_ADDRESS_MAP_APB_MISC_BASE + 0x84);
         val &= 0xFFFFFFF3;                                      /* 0 = UART */
         NV_WRITE32((NV_ADDRESS_MAP_APB_MISC_BASE + 0x84), val);
         debug("spi_init: PinMuxRegB = %08x\n", val);
 
         /* On Seaboard, MOSI/MISO are shared w/UART.
          * GPIO I3 (UART_DISABLE) was used to tristate UART in cs_activate.
          * Enable UART here by setting that GPIO to 0 so we can do U-Boot comms.
          */
 
          tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 0);
          debug("spi_cs_deactivate: ENABLED UART!\n");
         /*
          * CS is negated on Tegra, so drive a 0 to get a 1
         */
         spi->command &= ~SPI_CMD_CS_VAL;
 
         debug("spi_cs_deactivate: CS driven %s\n",
          (spi->command & SPI_CMD_CS_VAL) ? "LOW" : "HIGH");
+
+#ifdef CONFIG_SPI_CORRUPTS_UART
+        udelay(100);
+        NS16550_clear(CONFIG_SPI_CORRUPTS_UART);
+#endif
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
                 void *din, unsigned long flags)
 {
         volatile spi_tegra_t *spi = (spi_tegra_t *)TEGRA2_SPI_BASE;
         unsigned int tmpdin, status;
         int numBytes = (bitlen + 7) / 8;
         int ret, tm, isRead = 0;
 
@@ skipping 100 matching lines @@
                 spi->status = status;                   /* ACK RDY, etc. bits */
         }
 
         if (flags & SPI_XFER_END)
                 spi_cs_deactivate(slave);
 
         debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
          tmpdin, status);
         return ret;
 }