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Unified Diff: src/arm/assembler-arm.cc

Issue 6713074: Require an isolate parameter for most external reference creation to (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Further cleanup Created 9 years, 9 months ago
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Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index b57602c4e04c82558843599e00033e1e5cd2c119..be34df9c14411bcd2ac6aa7b4530988ff5218be8 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -269,19 +269,19 @@ static const int kMinimalBufferSize = 4*KB;
Assembler::Assembler(void* buffer, int buffer_size)
- : positions_recorder_(this),
+ : AssemblerBase(Isolate::Current()),
+ positions_recorder_(this),
allow_peephole_optimization_(false),
emit_debug_code_(FLAG_debug_code) {
- Isolate* isolate = Isolate::Current();
allow_peephole_optimization_ = FLAG_peephole_optimization;
if (buffer == NULL) {
// Do our own buffer management.
if (buffer_size <= kMinimalBufferSize) {
buffer_size = kMinimalBufferSize;
- if (isolate->assembler_spare_buffer() != NULL) {
- buffer = isolate->assembler_spare_buffer();
- isolate->set_assembler_spare_buffer(NULL);
+ if (isolate()->assembler_spare_buffer() != NULL) {
+ buffer = isolate()->assembler_spare_buffer();
+ isolate()->set_assembler_spare_buffer(NULL);
}
}
if (buffer == NULL) {
@@ -314,12 +314,11 @@ Assembler::Assembler(void* buffer, int buffer_size)
Assembler::~Assembler() {
- Isolate* isolate = Isolate::Current();
ASSERT(const_pool_blocked_nesting_ == 0);
if (own_buffer_) {
- if (isolate->assembler_spare_buffer() == NULL &&
+ if (isolate()->assembler_spare_buffer() == NULL &&
buffer_size_ == kMinimalBufferSize) {
- isolate->set_assembler_spare_buffer(buffer_);
+ isolate()->set_assembler_spare_buffer(buffer_);
} else {
DeleteArray(buffer_);
}
@@ -823,7 +822,7 @@ void Assembler::addrmod1(Instr instr,
Condition cond = Instruction::ConditionField(instr);
if ((instr & ~kCondMask) == 13*B21) { // mov, S not set
if (x.must_use_constant_pool() ||
- !Isolate::Current()->cpu_features()->IsSupported(ARMv7)) {
+ !isolate()->cpu_features()->IsSupported(ARMv7)) {
RecordRelocInfo(x.rmode_, x.imm32_);
ldr(rd, MemOperand(pc, 0), cond);
} else {
@@ -1266,7 +1265,7 @@ void Assembler::usat(Register dst,
const Operand& src,
Condition cond) {
// v6 and above.
- ASSERT(Isolate::Current()->cpu_features()->IsSupported(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsSupported(ARMv7));
ASSERT(!dst.is(pc) && !src.rm_.is(pc));
ASSERT((satpos >= 0) && (satpos <= 31));
ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL));
@@ -1294,7 +1293,7 @@ void Assembler::ubfx(Register dst,
int width,
Condition cond) {
// v7 and above.
- ASSERT(Isolate::Current()->cpu_features()->IsSupported(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsSupported(ARMv7));
ASSERT(!dst.is(pc) && !src.is(pc));
ASSERT((lsb >= 0) && (lsb <= 31));
ASSERT((width >= 1) && (width <= (32 - lsb)));
@@ -1314,7 +1313,7 @@ void Assembler::sbfx(Register dst,
int width,
Condition cond) {
// v7 and above.
- ASSERT(Isolate::Current()->cpu_features()->IsSupported(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsSupported(ARMv7));
ASSERT(!dst.is(pc) && !src.is(pc));
ASSERT((lsb >= 0) && (lsb <= 31));
ASSERT((width >= 1) && (width <= (32 - lsb)));
@@ -1329,7 +1328,7 @@ void Assembler::sbfx(Register dst,
// bfc dst, #lsb, #width
void Assembler::bfc(Register dst, int lsb, int width, Condition cond) {
// v7 and above.
- ASSERT(Isolate::Current()->cpu_features()->IsSupported(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsSupported(ARMv7));
ASSERT(!dst.is(pc));
ASSERT((lsb >= 0) && (lsb <= 31));
ASSERT((width >= 1) && (width <= (32 - lsb)));
@@ -1348,7 +1347,7 @@ void Assembler::bfi(Register dst,
int width,
Condition cond) {
// v7 and above.
- ASSERT(Isolate::Current()->cpu_features()->IsSupported(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsSupported(ARMv7));
ASSERT(!dst.is(pc) && !src.is(pc));
ASSERT((lsb >= 0) && (lsb <= 31));
ASSERT((width >= 1) && (width <= (32 - lsb)));
@@ -1620,7 +1619,7 @@ void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
void Assembler::ldrd(Register dst1, Register dst2,
const MemOperand& src, Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsEnabled(ARMv7));
ASSERT(src.rm().is(no_reg));
ASSERT(!dst1.is(lr)); // r14.
ASSERT_EQ(0, dst1.code() % 2);
@@ -1635,7 +1634,7 @@ void Assembler::strd(Register src1, Register src2,
ASSERT(!src1.is(lr)); // r14.
ASSERT_EQ(0, src1.code() % 2);
ASSERT_EQ(src1.code() + 1, src2.code());
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(ARMv7));
+ ASSERT(isolate()->cpu_features()->IsEnabled(ARMv7));
addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
}
@@ -1871,7 +1870,7 @@ void Assembler::vldr(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-628.
// cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) |
// Vdst(15-12) | 1011(11-8) | offset
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
int u = 1;
if (offset < 0) {
offset = -offset;
@@ -1913,7 +1912,7 @@ void Assembler::vldr(const SwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-628.
// cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) |
// Vdst(15-12) | 1010(11-8) | offset
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
int u = 1;
if (offset < 0) {
offset = -offset;
@@ -1957,7 +1956,7 @@ void Assembler::vstr(const DwVfpRegister src,
// Instruction details available in ARM DDI 0406A, A8-786.
// cond(31-28) | 1101(27-24)| U000(23-20) | | Rbase(19-16) |
// Vsrc(15-12) | 1011(11-8) | (offset/4)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
int u = 1;
if (offset < 0) {
offset = -offset;
@@ -1998,7 +1997,7 @@ void Assembler::vstr(const SwVfpRegister src,
// Instruction details available in ARM DDI 0406A, A8-786.
// cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) |
// Vdst(15-12) | 1010(11-8) | (offset/4)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
int u = 1;
if (offset < 0) {
offset = -offset;
@@ -2097,7 +2096,7 @@ void Assembler::vmov(const DwVfpRegister dst,
const Condition cond) {
// Dd = immediate
// Instruction details available in ARM DDI 0406B, A8-640.
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
uint32_t enc;
if (FitsVMOVDoubleImmediate(imm, &enc)) {
@@ -2134,7 +2133,7 @@ void Assembler::vmov(const SwVfpRegister dst,
const Condition cond) {
// Sd = Sm
// Instruction details available in ARM DDI 0406B, A8-642.
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
int sd, d, sm, m;
dst.split_code(&sd, &d);
src.split_code(&sm, &m);
@@ -2147,7 +2146,7 @@ void Assembler::vmov(const DwVfpRegister dst,
const Condition cond) {
// Dd = Dm
// Instruction details available in ARM DDI 0406B, A8-642.
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0xB*B20 |
dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code());
}
@@ -2161,7 +2160,7 @@ void Assembler::vmov(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-646.
// cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
// Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
ASSERT(!src1.is(pc) && !src2.is(pc));
emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
src1.code()*B12 | 0xB*B8 | B4 | dst.code());
@@ -2176,7 +2175,7 @@ void Assembler::vmov(const Register dst1,
// Instruction details available in ARM DDI 0406A, A8-646.
// cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
// Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
ASSERT(!dst1.is(pc) && !dst2.is(pc));
emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 |
dst1.code()*B12 | 0xB*B8 | B4 | src.code());
@@ -2190,7 +2189,7 @@ void Assembler::vmov(const SwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-642.
// cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
// Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
ASSERT(!src.is(pc));
int sn, n;
dst.split_code(&sn, &n);
@@ -2205,7 +2204,7 @@ void Assembler::vmov(const Register dst,
// Instruction details available in ARM DDI 0406A, A8-642.
// cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
// Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
ASSERT(!dst.is(pc));
int sn, n;
src.split_code(&sn, &n);
@@ -2330,7 +2329,7 @@ void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
const SwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
}
@@ -2339,7 +2338,7 @@ void Assembler::vcvt_f32_s32(const SwVfpRegister dst,
const SwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond));
}
@@ -2348,7 +2347,7 @@ void Assembler::vcvt_f64_u32(const DwVfpRegister dst,
const SwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
}
@@ -2357,7 +2356,7 @@ void Assembler::vcvt_s32_f64(const SwVfpRegister dst,
const DwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond));
}
@@ -2366,7 +2365,7 @@ void Assembler::vcvt_u32_f64(const SwVfpRegister dst,
const DwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond));
}
@@ -2375,7 +2374,7 @@ void Assembler::vcvt_f64_f32(const DwVfpRegister dst,
const SwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond));
}
@@ -2384,7 +2383,7 @@ void Assembler::vcvt_f32_f64(const SwVfpRegister dst,
const DwVfpRegister src,
VFPConversionMode mode,
const Condition cond) {
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
}
@@ -2414,7 +2413,7 @@ void Assembler::vadd(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-536.
// cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
}
@@ -2429,7 +2428,7 @@ void Assembler::vsub(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-784.
// cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
}
@@ -2444,7 +2443,7 @@ void Assembler::vmul(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-784.
// cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
}
@@ -2459,7 +2458,7 @@ void Assembler::vdiv(const DwVfpRegister dst,
// Instruction details available in ARM DDI 0406A, A8-584.
// cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
}
@@ -2472,7 +2471,7 @@ void Assembler::vcmp(const DwVfpRegister src1,
// Instruction details available in ARM DDI 0406A, A8-570.
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
}
@@ -2485,7 +2484,7 @@ void Assembler::vcmp(const DwVfpRegister src1,
// Instruction details available in ARM DDI 0406A, A8-570.
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | 0000(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
ASSERT(src2 == 0.0);
emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 |
src1.code()*B12 | 0x5*B9 | B8 | B6);
@@ -2496,7 +2495,7 @@ void Assembler::vmsr(Register dst, Condition cond) {
// Instruction details available in ARM DDI 0406A, A8-652.
// cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) |
// Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0xE*B20 | B16 |
dst.code()*B12 | 0xA*B8 | B4);
}
@@ -2506,7 +2505,7 @@ void Assembler::vmrs(Register dst, Condition cond) {
// Instruction details available in ARM DDI 0406A, A8-652.
// cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
// Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | 0xF*B20 | B16 |
dst.code()*B12 | 0xA*B8 | B4);
}
@@ -2517,7 +2516,7 @@ void Assembler::vsqrt(const DwVfpRegister dst,
const Condition cond) {
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0)
- ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
+ ASSERT(isolate()->cpu_features()->IsEnabled(VFP3));
emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 |
dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code());
}
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