ichspi.c: lower down the ICH7 chipset CDS timeout from 60s to 1ms.

ichspi.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
  * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
  * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
  * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
  * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
@@ skipping 553 matching lines @@
                 break;
         }
 
         /* Start */
         temp16 |= SPIC_SCGO;
 
         /* write it */
         REGWRITE16(ICH7_REG_SPIC, temp16);
 
         /* wait for cycle complete */
-        timeout = 100 * 1000 * 60;      // 60s is a looong timeout.
+        /* reduce timeout from 60 secs to 1 msec.
+         * Formula: for the largest possible data length on SPI bus:
+         *   page read/write: Instruction (1B) + Address (3B) + data (256B)
+         *   bit count = (1+3+256) * 8 = 2080

[dhendrix, 2011/03/15 19:30:38]

The longest instruction, JEDEC_AAI_WORD_PROGRAM, is 6 bytes long (1B opcode + 3B
initial address + 2B data for the initial address and initial address + 1).

I'm also not sure if it's good to assume 256 for the max data length. While this
is true for some chips, those which support auto address increment (AAI) such as
the SST25VF080 allow all bytes on the chip to be written without re-issuing an
instruction using a new address.

+         *   clock freq = 33MHz

[dhendrix, 2011/03/15 19:30:38]

SPI_CLK on the ICH7/NM10 is 17.86MHz according to the NM10 spec.

+         *   time needed: 2080 / 33Mhz = 63us
+         */
+        timeout = 100;
         while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
                 programmer_delay(10);
         }
         if (!timeout) {
-                msg_perr("timeout\n");
+                msg_perr("ICH7 CDS timeout\n");
         }
 
         /* FIXME: make sure we do not needlessly cause transaction errors. */
         if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
                 msg_pdbg("Transaction error!\n");
                 return 1;
         }
 
         if ((!write_cmd) && (datalength != 0)) {
                 for (a = 0; a < datalength; a++) {
@@ skipping 578 matching lines @@
                 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
                 ichspi_lock = 1;
         }
 
         ich_init_opcodes();
 
         return 0;
 }
 
 #endif