ARM: Add support load/store multiple VFP registers

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index 899b88a6d3399b2736b4aaeb17cb57ef17b292e7..ee9f3f4bc45bf2e23134d15d2e99537b140514bf 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -383,9 +383,15 @@ int Decoder::FormatVFPRegister(Instruction* instr, const char* format) {
     return 2;
   } else if (format[1] == 'd') {
     int reg = instr->VdValue();
-    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DValue()));
+    if (format[0] == 'S') reg = reg << 1 | instr->DValue();

[Rodolph Perfetta, 2011/04/05 18:16:39]

Using instr->VFPDRegValue(kSinglePrecision) would simplify the code. Could also
be reused above.

[Søren Thygesen Gjesse, 2011/04/06 08:00:09]

Changed to use instr->VFPXRegValue (X=M|M|D) in all cases and refactored a bit.

+    if (format[2] == '+') {
+      int immed8 = instr->Immed8Value();
+      if (format[0] == 'S') reg += immed8 - 1;
+      if (format[0] == 'D') reg += (immed8 / 2 - 1);
+    }
+    if (format[0] == 'S') PrintSRegister(reg);
     if (format[0] == 'D') PrintDRegister(reg);
-    return 2;
+    return format[2] == '+' ? 3 : 2;
   }
 
   UNREACHABLE();
@@ -1273,9 +1279,22 @@ void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
           Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
         }
         break;
-      default:
-        Unknown(instr);  // Not used by V8.
+      default: {

[Rodolph Perfetta, 2011/04/05 18:16:39]

VLDM/VSTM covers cases 0x4-0x7, 0x9, 0xB for single precision. Some cases are
undefined instructions (P==U, W==0)

[Søren Thygesen Gjesse, 2011/04/06 08:00:09]

Changed to use 6 explicit case values and default as before.

+        BlockAddrMode am =
+            static_cast<BlockAddrMode>(
+                instr->BitField(24, 21) & kBlockAddrModeMask);
+        if (am == ia || am == ia_w || am == db_w) {
+          bool to_arm_register = (instr->VLValue() == 0x1);

[Rodolph Perfetta, 2011/04/05 18:16:39]

This variable has a confusing name. It sounds like you're using vldm to load
into an ARM (rather than VFP) register.

[Søren Thygesen Gjesse, 2011/04/06 08:00:09]

Changed to to_vfp_regsiter.

+          if (to_arm_register) {
+            Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}");
+          } else {
+            Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}");
+          }
+        } else {
+          Unknown(instr);  // Not used by V8.
+        }
         break;
+      }
     }
   } else if (instr->CoprocessorValue() == 0xB) {
     switch (instr->OpcodeValue()) {
@@ -1303,9 +1322,22 @@ void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
           Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]");
         }
         break;
-      default:
-        Unknown(instr);  // Not used by V8.
+      default: {

[Rodolph Perfetta, 2011/04/05 18:16:39]

VLDM/VSTM covers cases 0x4, 0x5, 0x9 for double precision in V8. The difference
between single and double precision cases is caused by V8 supporting 16
D-registers (removing cases 0x6, 0x7, 0xB.)

[Søren Thygesen Gjesse, 2011/04/06 08:00:09]

Changed to use 3 explicit case values and default as before.

+        BlockAddrMode am =
+            static_cast<BlockAddrMode>(
+                instr->BitField(24, 21) & kBlockAddrModeMask);
+        if (am == ia || am == ia_w || am == db_w) {
+          bool to_arm_register = (instr->VLValue() == 0x1);
+          if (to_arm_register) {
+            Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}");
+          } else {
+            Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}");
+          }
+        } else {
+          Unknown(instr);  // Not used by V8.
+        }
         break;
+      }
     }
   } else {
     Unknown(instr);  // Not used by V8.