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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
11 // with the distribution. | 11 // with the distribution. |
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364 UNREACHABLE(); | 364 UNREACHABLE(); |
365 return -1; | 365 return -1; |
366 } | 366 } |
367 | 367 |
368 | 368 |
369 // Handle all VFP register based formatting in this function to reduce the | 369 // Handle all VFP register based formatting in this function to reduce the |
370 // complexity of FormatOption. | 370 // complexity of FormatOption. |
371 int Decoder::FormatVFPRegister(Instruction* instr, const char* format) { | 371 int Decoder::FormatVFPRegister(Instruction* instr, const char* format) { |
372 ASSERT((format[0] == 'S') || (format[0] == 'D')); | 372 ASSERT((format[0] == 'S') || (format[0] == 'D')); |
373 | 373 |
| 374 VFPRegPrecision precision = |
| 375 format[0] == 'D' ? kDoublePrecision : kSinglePrecision; |
| 376 |
| 377 int retval = 2; |
| 378 int reg = -1; |
374 if (format[1] == 'n') { | 379 if (format[1] == 'n') { |
375 int reg = instr->VnValue(); | 380 reg = instr->VFPNRegValue(precision); |
376 if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NValue())); | |
377 if (format[0] == 'D') PrintDRegister(reg); | |
378 return 2; | |
379 } else if (format[1] == 'm') { | 381 } else if (format[1] == 'm') { |
380 int reg = instr->VmValue(); | 382 reg = instr->VFPMRegValue(precision); |
381 if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MValue())); | |
382 if (format[0] == 'D') PrintDRegister(reg); | |
383 return 2; | |
384 } else if (format[1] == 'd') { | 383 } else if (format[1] == 'd') { |
385 int reg = instr->VdValue(); | 384 reg = instr->VFPDRegValue(precision); |
386 if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DValue())); | 385 if (format[2] == '+') { |
387 if (format[0] == 'D') PrintDRegister(reg); | 386 int immed8 = instr->Immed8Value(); |
388 return 2; | 387 if (format[0] == 'S') reg += immed8 - 1; |
| 388 if (format[0] == 'D') reg += (immed8 / 2 - 1); |
| 389 } |
| 390 if (format[2] == '+') retval = 3; |
| 391 } else { |
| 392 UNREACHABLE(); |
389 } | 393 } |
390 | 394 |
391 UNREACHABLE(); | 395 if (precision == kSinglePrecision) { |
392 return -1; | 396 PrintSRegister(reg); |
| 397 } else { |
| 398 PrintDRegister(reg); |
| 399 } |
| 400 |
| 401 return retval; |
393 } | 402 } |
394 | 403 |
395 | 404 |
396 int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) { | 405 int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) { |
397 Print(format); | 406 Print(format); |
398 return 0; | 407 return 0; |
399 } | 408 } |
400 | 409 |
401 | 410 |
402 // Print the movw or movt instruction. | 411 // Print the movw or movt instruction. |
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1266 } | 1275 } |
1267 break; | 1276 break; |
1268 case 0xC: | 1277 case 0xC: |
1269 case 0xE: | 1278 case 0xE: |
1270 if (instr->HasL()) { | 1279 if (instr->HasL()) { |
1271 Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]"); | 1280 Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]"); |
1272 } else { | 1281 } else { |
1273 Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]"); | 1282 Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]"); |
1274 } | 1283 } |
1275 break; | 1284 break; |
| 1285 case 0x4: |
| 1286 case 0x5: |
| 1287 case 0x6: |
| 1288 case 0x7: |
| 1289 case 0x9: |
| 1290 case 0xB: { |
| 1291 bool to_vfp_register = (instr->VLValue() == 0x1); |
| 1292 if (to_vfp_register) { |
| 1293 Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}"); |
| 1294 } else { |
| 1295 Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}"); |
| 1296 } |
| 1297 break; |
| 1298 } |
1276 default: | 1299 default: |
1277 Unknown(instr); // Not used by V8. | 1300 Unknown(instr); // Not used by V8. |
1278 break; | |
1279 } | 1301 } |
1280 } else if (instr->CoprocessorValue() == 0xB) { | 1302 } else if (instr->CoprocessorValue() == 0xB) { |
1281 switch (instr->OpcodeValue()) { | 1303 switch (instr->OpcodeValue()) { |
1282 case 0x2: | 1304 case 0x2: |
1283 // Load and store double to two GP registers | 1305 // Load and store double to two GP registers |
1284 if (instr->Bits(7, 4) != 0x1) { | 1306 if (instr->Bits(7, 4) != 0x1) { |
1285 Unknown(instr); // Not used by V8. | 1307 Unknown(instr); // Not used by V8. |
1286 } else if (instr->HasL()) { | 1308 } else if (instr->HasL()) { |
1287 Format(instr, "vmov'cond 'rt, 'rn, 'Dm"); | 1309 Format(instr, "vmov'cond 'rt, 'rn, 'Dm"); |
1288 } else { | 1310 } else { |
1289 Format(instr, "vmov'cond 'Dm, 'rt, 'rn"); | 1311 Format(instr, "vmov'cond 'Dm, 'rt, 'rn"); |
1290 } | 1312 } |
1291 break; | 1313 break; |
1292 case 0x8: | 1314 case 0x8: |
1293 if (instr->HasL()) { | 1315 if (instr->HasL()) { |
1294 Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]"); | 1316 Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]"); |
1295 } else { | 1317 } else { |
1296 Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]"); | 1318 Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]"); |
1297 } | 1319 } |
1298 break; | 1320 break; |
1299 case 0xC: | 1321 case 0xC: |
1300 if (instr->HasL()) { | 1322 if (instr->HasL()) { |
1301 Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]"); | 1323 Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]"); |
1302 } else { | 1324 } else { |
1303 Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]"); | 1325 Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]"); |
1304 } | 1326 } |
1305 break; | 1327 break; |
| 1328 case 0x4: |
| 1329 case 0x5: |
| 1330 case 0x9: { |
| 1331 bool to_vfp_register = (instr->VLValue() == 0x1); |
| 1332 if (to_vfp_register) { |
| 1333 Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}"); |
| 1334 } else { |
| 1335 Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}"); |
| 1336 } |
| 1337 break; |
| 1338 } |
1306 default: | 1339 default: |
1307 Unknown(instr); // Not used by V8. | 1340 Unknown(instr); // Not used by V8. |
1308 break; | |
1309 } | 1341 } |
1310 } else { | 1342 } else { |
1311 Unknown(instr); // Not used by V8. | 1343 Unknown(instr); // Not used by V8. |
1312 } | 1344 } |
1313 } | 1345 } |
1314 | 1346 |
1315 | 1347 |
1316 bool Decoder::IsConstantPoolAt(byte* instr_ptr) { | 1348 bool Decoder::IsConstantPoolAt(byte* instr_ptr) { |
1317 int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); | 1349 int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); |
1318 return (instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker; | 1350 return (instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker; |
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1462 pc += d.InstructionDecode(buffer, pc); | 1494 pc += d.InstructionDecode(buffer, pc); |
1463 fprintf(f, "%p %08x %s\n", | 1495 fprintf(f, "%p %08x %s\n", |
1464 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1496 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1465 } | 1497 } |
1466 } | 1498 } |
1467 | 1499 |
1468 | 1500 |
1469 } // namespace disasm | 1501 } // namespace disasm |
1470 | 1502 |
1471 #endif // V8_TARGET_ARCH_ARM | 1503 #endif // V8_TARGET_ARCH_ARM |
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