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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | 25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | 26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | 28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
31 // OF THE POSSIBILITY OF SUCH DAMAGE. | 31 // OF THE POSSIBILITY OF SUCH DAMAGE. |
32 | 32 |
33 // The original source code covered by the above license above has been | 33 // The original source code covered by the above license above has been |
34 // modified significantly by Google Inc. | 34 // modified significantly by Google Inc. |
35 // Copyright 2010 the V8 project authors. All rights reserved. | 35 // Copyright 2011 the V8 project authors. All rights reserved. |
36 | 36 |
37 #include "v8.h" | 37 #include "v8.h" |
38 | 38 |
39 #if defined(V8_TARGET_ARCH_ARM) | 39 #if defined(V8_TARGET_ARCH_ARM) |
40 | 40 |
41 #include "arm/assembler-arm-inl.h" | 41 #include "arm/assembler-arm-inl.h" |
42 #include "serialize.h" | 42 #include "serialize.h" |
43 | 43 |
44 namespace v8 { | 44 namespace v8 { |
45 namespace internal { | 45 namespace internal { |
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2028 | 2028 |
2029 void Assembler::vstr(const SwVfpRegister src, | 2029 void Assembler::vstr(const SwVfpRegister src, |
2030 const MemOperand& operand, | 2030 const MemOperand& operand, |
2031 const Condition cond) { | 2031 const Condition cond) { |
2032 ASSERT(!operand.rm().is_valid()); | 2032 ASSERT(!operand.rm().is_valid()); |
2033 ASSERT(operand.am_ == Offset); | 2033 ASSERT(operand.am_ == Offset); |
2034 vldr(src, operand.rn(), operand.offset(), cond); | 2034 vldr(src, operand.rn(), operand.offset(), cond); |
2035 } | 2035 } |
2036 | 2036 |
2037 | 2037 |
| 2038 void Assembler::vldm(BlockAddrMode am, |
| 2039 Register base, |
| 2040 DwVfpRegister first, |
| 2041 DwVfpRegister last, |
| 2042 Condition cond) { |
| 2043 // Instruction details available in ARM DDI 0406A, A8-626. |
| 2044 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
| 2045 // first(15-12) | 1010(11-8) | (count * 2) |
| 2046 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2047 ASSERT_LE(first.code(), last.code()); |
| 2048 ASSERT(am == ia || am == ia_w || am == db_w); |
| 2049 ASSERT(!base.is(pc)); |
| 2050 |
| 2051 int sd, d; |
| 2052 first.split_code(&sd, &d); |
| 2053 int count = last.code() - first.code() + 1; |
| 2054 emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 2055 0xB*B8 | count*2); |
| 2056 } |
| 2057 |
| 2058 |
| 2059 void Assembler::vstm(BlockAddrMode am, |
| 2060 Register base, |
| 2061 DwVfpRegister first, |
| 2062 DwVfpRegister last, |
| 2063 Condition cond) { |
| 2064 // Instruction details available in ARM DDI 0406A, A8-784. |
| 2065 // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 2066 // first(15-12) | 1011(11-8) | (count * 2) |
| 2067 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2068 ASSERT_LE(first.code(), last.code()); |
| 2069 ASSERT(am == ia || am == ia_w || am == db_w); |
| 2070 ASSERT(!base.is(pc)); |
| 2071 |
| 2072 int sd, d; |
| 2073 first.split_code(&sd, &d); |
| 2074 int count = last.code() - first.code() + 1; |
| 2075 emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 2076 0xB*B8 | count*2); |
| 2077 } |
| 2078 |
| 2079 void Assembler::vldm(BlockAddrMode am, |
| 2080 Register base, |
| 2081 SwVfpRegister first, |
| 2082 SwVfpRegister last, |
| 2083 Condition cond) { |
| 2084 // Instruction details available in ARM DDI 0406A, A8-626. |
| 2085 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
| 2086 // first(15-12) | 1010(11-8) | (count/2) |
| 2087 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2088 ASSERT_LE(first.code(), last.code()); |
| 2089 ASSERT(am == ia || am == ia_w || am == db_w); |
| 2090 ASSERT(!base.is(pc)); |
| 2091 |
| 2092 int sd, d; |
| 2093 first.split_code(&sd, &d); |
| 2094 int count = last.code() - first.code() + 1; |
| 2095 emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 2096 0xA*B8 | count); |
| 2097 } |
| 2098 |
| 2099 |
| 2100 void Assembler::vstm(BlockAddrMode am, |
| 2101 Register base, |
| 2102 SwVfpRegister first, |
| 2103 SwVfpRegister last, |
| 2104 Condition cond) { |
| 2105 // Instruction details available in ARM DDI 0406A, A8-784. |
| 2106 // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 2107 // first(15-12) | 1011(11-8) | (count/2) |
| 2108 ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2109 ASSERT_LE(first.code(), last.code()); |
| 2110 ASSERT(am == ia || am == ia_w || am == db_w); |
| 2111 ASSERT(!base.is(pc)); |
| 2112 |
| 2113 int sd, d; |
| 2114 first.split_code(&sd, &d); |
| 2115 int count = last.code() - first.code() + 1; |
| 2116 emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 2117 0xA*B8 | count); |
| 2118 } |
| 2119 |
2038 static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { | 2120 static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { |
2039 uint64_t i; | 2121 uint64_t i; |
2040 memcpy(&i, &d, 8); | 2122 memcpy(&i, &d, 8); |
2041 | 2123 |
2042 *lo = i & 0xffffffff; | 2124 *lo = i & 0xffffffff; |
2043 *hi = i >> 32; | 2125 *hi = i >> 32; |
2044 } | 2126 } |
2045 | 2127 |
2046 // Only works for little endian floating point formats. | 2128 // Only works for little endian floating point formats. |
2047 // We don't support VFP on the mixed endian floating point platform. | 2129 // We don't support VFP on the mixed endian floating point platform. |
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2786 | 2868 |
2787 // Since a constant pool was just emitted, move the check offset forward by | 2869 // Since a constant pool was just emitted, move the check offset forward by |
2788 // the standard interval. | 2870 // the standard interval. |
2789 next_buffer_check_ = pc_offset() + kCheckConstInterval; | 2871 next_buffer_check_ = pc_offset() + kCheckConstInterval; |
2790 } | 2872 } |
2791 | 2873 |
2792 | 2874 |
2793 } } // namespace v8::internal | 2875 } } // namespace v8::internal |
2794 | 2876 |
2795 #endif // V8_TARGET_ARCH_ARM | 2877 #endif // V8_TARGET_ARCH_ARM |
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