Merge isolates to bleeding_edge.

test/cctest/test-disasm-arm.cc

 // Copyright 2007-2008 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 252 matching lines @@
   COMPARE(mvn(r3, Operand(-1), LeaveCC, al),
           "e3a03000       mov r3, #0");
   COMPARE(mvn(r4, Operand(-2), SetCC, al),
           "e3b04001       movs r4, #1");
   COMPARE(mvn(r5, Operand(0x0ffffff0), SetCC, ne),
           "13b052ff       movnes r5, #-268435441");
   COMPARE(mvn(r6, Operand(-1), LeaveCC, ne),
           "13a06000       movne r6, #0");
 
   // mov -> movw.
-  if (CpuFeatures::IsSupported(ARMv7)) {
+  if (Isolate::Current()->cpu_features()->IsSupported(ARMv7)) {
     COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne),
             "13015234       movwne r5, #4660");
     // We only disassemble one instruction so the eor instruction is not here.
     COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
             "1301c234       movwne ip, #4660");
     // Movw can't do setcc so we don't get that here.  Mov immediate with setcc
     // is pretty strange anyway.
     COMPARE(mov(r5, Operand(0x01234), SetCC, ne),
             "159fc000       ldrne ip, [pc, #+0]");
     // We only disassemble one instruction so the eor instruction is not here.
@@ skipping 69 matching lines @@
   COMPARE(eor(r4, r1, Operand(0x10000000), SetCC, cc),
           "32314201       eorccs r4, r1, #268435456");
 
   VERIFY_RUN();
 }
 
 
 TEST(Type3) {
   SETUP();
 
-  if (CpuFeatures::IsSupported(ARMv7)) {
+  if (Isolate::Current()->cpu_features()->IsSupported(ARMv7)) {
     COMPARE(ubfx(r0, r1, 5, 10),
             "e7e902d1       ubfx r0, r1, #5, #10");
     COMPARE(ubfx(r1, r0, 5, 10),
             "e7e912d0       ubfx r1, r0, #5, #10");
     COMPARE(ubfx(r0, r1, 31, 1),
             "e7e00fd1       ubfx r0, r1, #31, #1");
     COMPARE(ubfx(r1, r0, 31, 1),
             "e7e01fd0       ubfx r1, r0, #31, #1");
 
     COMPARE(sbfx(r0, r1, 5, 10),
@@ skipping 34 matching lines @@
   }
 
   VERIFY_RUN();
 }
 
 
 
 TEST(Vfp) {
   SETUP();
 
-  if (CpuFeatures::IsSupported(VFP3)) {
+  if (Isolate::Current()->cpu_features()->IsSupported(VFP3)) {
     CpuFeatures::Scope scope(VFP3);
     COMPARE(vmov(d0, d1),
             "eeb00b41       vmov.f64 d0, d1");
     COMPARE(vmov(d3, d3, eq),
             "0eb03b43       vmov.f64eq d3, d3");
 
     COMPARE(vmov(s0, s31),
             "eeb00a6f       vmov.f32 s0, s31");
     COMPARE(vmov(s31, s0),
             "eef0fa40       vmov.f32 s31, s0");
@@ skipping 90 matching lines @@
     COMPARE(vmrs(r5),
             "eef15a10       vmrs r5, FPSCR");
     COMPARE(vmrs(r10, ge),
             "aef1aa10       vmrsge r10, FPSCR");
     COMPARE(vmrs(pc),
             "eef1fa10       vmrs APSR, FPSCR");
   }
 
   VERIFY_RUN();
 }