OLD | NEW |
1 /** | 1 /** |
2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. | 2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. |
3 * | 3 * |
4 * See file CREDITS for list of people who contributed to this | 4 * See file CREDITS for list of people who contributed to this |
5 * project. | 5 * project. |
6 * | 6 * |
7 * This program is free software; you can redistribute it and/or | 7 * This program is free software; you can redistribute it and/or |
8 * modify it under the terms of the GNU General Public License as | 8 * modify it under the terms of the GNU General Public License as |
9 * published by the Free Software Foundation; either version 2 of | 9 * published by the Free Software Foundation; either version 2 of |
10 * the License, or (at your option) any later version. | 10 * the License, or (at your option) any later version. |
11 * | 11 * |
12 * This program is distributed in the hope that it will be useful, | 12 * This program is distributed in the hope that it will be useful, |
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of | 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
15 * GNU General Public License for more details. | 15 * GNU General Public License for more details. |
16 * | 16 * |
17 * You should have received a copy of the GNU General Public License | 17 * You should have received a copy of the GNU General Public License |
18 * along with this program; if not, write to the Free Software | 18 * along with this program; if not, write to the Free Software |
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
20 * MA 02111-1307 USA | 20 * MA 02111-1307 USA |
21 */ | 21 */ |
22 | 22 |
23 #include "cbootimage.h" | 23 #include "cbootimage.h" |
24 #include "nvbctlib.h" | 24 #include "nvbctlib.h" |
25 #include "data_layout.h" | 25 #include "data_layout.h" |
26 #include "context.h" | 26 #include "context.h" |
| 27 #include "parse.h" |
27 | 28 |
28 #include <string.h> | 29 #include <string.h> |
29 | 30 |
30 int enable_debug = 0; | 31 int enable_debug = 0; |
31 | 32 |
32 typedef struct { | 33 typedef struct { |
33 nvbct_lib_id id; | 34 nvbct_lib_id id; |
34 char const * message; | 35 char const * message; |
35 } value_data; | 36 } value_data; |
36 | 37 |
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
71 {nvbct_lib_id_bl_length, | 72 {nvbct_lib_id_bl_length, |
72 " Length........: %d\n"}, | 73 " Length........: %d\n"}, |
73 {nvbct_lib_id_bl_load_addr, | 74 {nvbct_lib_id_bl_load_addr, |
74 " Load address..: 0x%08x\n"}, | 75 " Load address..: 0x%08x\n"}, |
75 {nvbct_lib_id_bl_entry_point, | 76 {nvbct_lib_id_bl_entry_point, |
76 " Entry point...: 0x%08x\n"}, | 77 " Entry point...: 0x%08x\n"}, |
77 {nvbct_lib_id_bl_attribute, | 78 {nvbct_lib_id_bl_attribute, |
78 " Attributes....: 0x%08x\n"}, | 79 " Attributes....: 0x%08x\n"}, |
79 }; | 80 }; |
80 | 81 |
81 static value_data const spi_values[] = { | |
82 {nvbct_lib_id_spiflash_read_command_type_fast, | |
83 " Command fast...: %d\n"}, | |
84 {nvbct_lib_id_spiflash_clock_source, | |
85 " Clock source...: %d\n"}, | |
86 {nvbct_lib_id_spiflash_clock_divider, | |
87 " Clock divider..: %d\n"}, | |
88 }; | |
89 | |
90 static value_data const sdmmc_values[] = { | |
91 {nvbct_lib_id_sdmmc_clock_divider, | |
92 " Clock divider..: %d\n"}, | |
93 {nvbct_lib_id_sdmmc_data_width, | |
94 " Data width.....: %d\n"}, | |
95 {nvbct_lib_id_sdmmc_max_power_class_supported, | |
96 " Power class....: %d\n"}, | |
97 }; | |
98 | |
99 static value_data const sdram_values[] = { | |
100 {nvbct_lib_id_sdram_pllm_charge_pump_setup_ctrl, | |
101 " PLLM_CHARGE_PUMP_SETUP_CTRL.....: 0x%08x\n"}, | |
102 {nvbct_lib_id_sdram_pllm_loop_filter_setup_ctrl, | |
103 " PLLM_LOOP_FILTER_SETUP_CTRL.....: 0x%08x\n"}, | |
104 {nvbct_lib_id_sdram_pllm_input_divider, | |
105 " PLLM_INPUT_DIVIDER..............: 0x%08x\n"}, | |
106 {nvbct_lib_id_sdram_pllm_feedback_divider, | |
107 " PLLM_FEEDBACK_DIVIDER...........: 0x%08x\n"}, | |
108 {nvbct_lib_id_sdram_pllm_post_divider, | |
109 " PLLM_POST_DIVIDER...............: 0x%08x\n"}, | |
110 {nvbct_lib_id_sdram_pllm_stable_time, | |
111 " PLLM_STABLE_TIME................: 0x%08x\n"}, | |
112 {nvbct_lib_id_sdram_emc_clock_divider, | |
113 " EMC_CLOCK_DIVIDER...............: 0x%08x\n"}, | |
114 {nvbct_lib_id_sdram_emc_auto_cal_interval, | |
115 " EMC_AUTO_CAL_INTERVAL...........: 0x%08x\n"}, | |
116 {nvbct_lib_id_sdram_emc_auto_cal_config, | |
117 " EMC_AUTO_CAL_CONFIG.............: 0x%08x\n"}, | |
118 {nvbct_lib_id_sdram_emc_auto_cal_wait, | |
119 " EMC_AUTO_CAL_WAIT...............: 0x%08x\n"}, | |
120 {nvbct_lib_id_sdram_emc_pin_program_wait, | |
121 " EMC_PIN_PROGRAM_WAIT............: 0x%08x\n"}, | |
122 {nvbct_lib_id_sdram_emc_rc, | |
123 " EMC_RC..........................: 0x%08x\n"}, | |
124 {nvbct_lib_id_sdram_emc_rfc, | |
125 " EMC_RFC.........................: 0x%08x\n"}, | |
126 {nvbct_lib_id_sdram_emc_ras, | |
127 " EMC_RAS.........................: 0x%08x\n"}, | |
128 {nvbct_lib_id_sdram_emc_rp, | |
129 " EMC_RP..........................: 0x%08x\n"}, | |
130 {nvbct_lib_id_sdram_emc_r2w, | |
131 " EMC_R2W.........................: 0x%08x\n"}, | |
132 {nvbct_lib_id_sdram_emc_w2r, | |
133 " EMC_W2R.........................: 0x%08x\n"}, | |
134 {nvbct_lib_id_sdram_emc_r2p, | |
135 " EMC_R2P.........................: 0x%08x\n"}, | |
136 {nvbct_lib_id_sdram_emc_w2p, | |
137 " EMC_W2P.........................: 0x%08x\n"}, | |
138 {nvbct_lib_id_sdram_emc_rd_rcd, | |
139 " EMC_RD_RCD......................: 0x%08x\n"}, | |
140 {nvbct_lib_id_sdram_emc_wr_rcd, | |
141 " EMC_WR_RCD......................: 0x%08x\n"}, | |
142 {nvbct_lib_id_sdram_emc_rrd, | |
143 " EMC_RRD.........................: 0x%08x\n"}, | |
144 {nvbct_lib_id_sdram_emc_rext, | |
145 " EMC_REXT........................: 0x%08x\n"}, | |
146 {nvbct_lib_id_sdram_emc_wdv, | |
147 " EMC_WDV.........................: 0x%08x\n"}, | |
148 {nvbct_lib_id_sdram_emc_quse, | |
149 " EMC_QUSE........................: 0x%08x\n"}, | |
150 {nvbct_lib_id_sdram_emc_qrst, | |
151 " EMC_QRST........................: 0x%08x\n"}, | |
152 {nvbct_lib_id_sdram_emc_qsafe, | |
153 " EMC_QSAFE.......................: 0x%08x\n"}, | |
154 {nvbct_lib_id_sdram_emc_rdv, | |
155 " EMC_RDV.........................: 0x%08x\n"}, | |
156 {nvbct_lib_id_sdram_emc_refresh, | |
157 " EMC_REFRESH.....................: 0x%08x\n"}, | |
158 {nvbct_lib_id_sdram_emc_burst_refresh_num, | |
159 " EMC_BURST_REFRESH_NUM...........: 0x%08x\n"}, | |
160 {nvbct_lib_id_sdram_emc_pdex2wr, | |
161 " EMC_PDEX2WR.....................: 0x%08x\n"}, | |
162 {nvbct_lib_id_sdram_emc_pdex2rd, | |
163 " EMC_PDEX2RD.....................: 0x%08x\n"}, | |
164 {nvbct_lib_id_sdram_emc_pchg2pden, | |
165 " EMC_PCHG2PDEN...................: 0x%08x\n"}, | |
166 {nvbct_lib_id_sdram_emc_act2pden, | |
167 " EMC_ACT2PDEN....................: 0x%08x\n"}, | |
168 {nvbct_lib_id_sdram_emc_ar2pden, | |
169 " EMC_AR2PDEN.....................: 0x%08x\n"}, | |
170 {nvbct_lib_id_sdram_emc_rw2pden, | |
171 " EMC_RW2PDEN.....................: 0x%08x\n"}, | |
172 {nvbct_lib_id_sdram_emc_txsr, | |
173 " EMC_TXSR........................: 0x%08x\n"}, | |
174 {nvbct_lib_id_sdram_emc_tcke, | |
175 " EMC_TCKE........................: 0x%08x\n"}, | |
176 {nvbct_lib_id_sdram_emc_tfaw, | |
177 " EMC_TFAW........................: 0x%08x\n"}, | |
178 {nvbct_lib_id_sdram_emc_trpab, | |
179 " EMC_TRPAB.......................: 0x%08x\n"}, | |
180 {nvbct_lib_id_sdram_emc_tclkstable, | |
181 " EMC_TCLKSTABLE..................: 0x%08x\n"}, | |
182 {nvbct_lib_id_sdram_emc_tclkstop, | |
183 " EMC_TCLKSTOP....................: 0x%08x\n"}, | |
184 {nvbct_lib_id_sdram_emc_trefbw, | |
185 " EMC_TREFBW......................: 0x%08x\n"}, | |
186 {nvbct_lib_id_sdram_emc_quse_extra, | |
187 " EMC_QUSE_EXTRA..................: 0x%08x\n"}, | |
188 {nvbct_lib_id_sdram_emc_fbio_cfg1, | |
189 " EMC_FBIO_CFG1...................: 0x%08x\n"}, | |
190 {nvbct_lib_id_sdram_emc_fbio_dqsib_dly, | |
191 " EMC_FBIO_DQSIB_DLY..............: 0x%08x\n"}, | |
192 {nvbct_lib_id_sdram_emc_fbio_dqsib_dly_msb, | |
193 " EMC_FBIO_DQSIB_DLY_MSB..........: 0x%08x\n"}, | |
194 {nvbct_lib_id_sdram_emc_fbio_quse_dly, | |
195 " EMC_FBIO_QUSE_DLY...............: 0x%08x\n"}, | |
196 {nvbct_lib_id_sdram_emc_fbio_quse_dly_msb, | |
197 " EMC_FBIO_QUSE_DLY_MSB...........: 0x%08x\n"}, | |
198 {nvbct_lib_id_sdram_emc_fbio_cfg5, | |
199 " EMC_FBIO_CFG5...................: 0x%08x\n"}, | |
200 {nvbct_lib_id_sdram_emc_fbio_cfg6, | |
201 " EMC_FBIO_CFG6...................: 0x%08x\n"}, | |
202 {nvbct_lib_id_sdram_emc_fbio_spare, | |
203 " EMC_FBIO_SPARE..................: 0x%08x\n"}, | |
204 {nvbct_lib_id_sdram_emc_mrs, | |
205 " EMC_MRS.........................: 0x%08x\n"}, | |
206 {nvbct_lib_id_sdram_emc_emrs, | |
207 " EMC_EMRS........................: 0x%08x\n"}, | |
208 {nvbct_lib_id_sdram_emc_mrw1, | |
209 " EMC_MRW1........................: 0x%08x\n"}, | |
210 {nvbct_lib_id_sdram_emc_mrw2, | |
211 " EMC_MRW2........................: 0x%08x\n"}, | |
212 {nvbct_lib_id_sdram_emc_mrw3, | |
213 " EMC_MRW3........................: 0x%08x\n"}, | |
214 {nvbct_lib_id_sdram_emc_mrw_reset_command, | |
215 " EMC_MRW_RESET_COMMAND...........: 0x%08x\n"}, | |
216 {nvbct_lib_id_sdram_emc_mrw_reset_ninit_wait, | |
217 " EMC_MRW_RESET_NINIT_WAIT........: 0x%08x\n"}, | |
218 {nvbct_lib_id_sdram_emc_adr_cfg, | |
219 " EMC_ADR_CFG.....................: 0x%08x\n"}, | |
220 {nvbct_lib_id_sdram_emc_adr_cfg1, | |
221 " EMC_ADR_CFG1....................: 0x%08x\n"}, | |
222 {nvbct_lib_id_sdram_mc_emem_Cfg, | |
223 " MC_EMEM_CFG.....................: 0x%08x\n"}, | |
224 {nvbct_lib_id_sdram_mc_lowlatency_config, | |
225 " MC_LOWLATENCY_CONFIG............: 0x%08x\n"}, | |
226 {nvbct_lib_id_sdram_emc_cfg, | |
227 " EMC_CFG.........................: 0x%08x\n"}, | |
228 {nvbct_lib_id_sdram_emc_cfg2, | |
229 " EMC_CFG2........................: 0x%08x\n"}, | |
230 {nvbct_lib_id_sdram_emc_dbg, | |
231 " EMC_DBG.........................: 0x%08x\n"}, | |
232 {nvbct_lib_id_sdram_ahb_arbitration_xbar_ctrl, | |
233 " AHB_ARBITRATION_XBAR_CTRL.......: 0x%08x\n"}, | |
234 {nvbct_lib_id_sdram_emc_cfg_dig_dll, | |
235 " EMC_CFG_DIG_DLL.................: 0x%08x\n"}, | |
236 {nvbct_lib_id_sdram_emc_dll_xform_dqs, | |
237 " EMC_DLL_XFORM_DQS...............: 0x%08x\n"}, | |
238 {nvbct_lib_id_sdram_emc_dll_xform_quse, | |
239 " EMC_DLL_XFORM_QUSE..............: 0x%08x\n"}, | |
240 {nvbct_lib_id_sdram_warm_boot_wait, | |
241 " WARM_BOOT_WAIT..................: 0x%08x\n"}, | |
242 {nvbct_lib_id_sdram_emc_ctt_term_ctrl, | |
243 " EMC_CTT_TERM_CTRL...............: 0x%08x\n"}, | |
244 {nvbct_lib_id_sdram_emc_odt_write, | |
245 " EMC_ODT_WRITE...................: 0x%08x\n"}, | |
246 {nvbct_lib_id_sdram_emc_odt_read, | |
247 " EMC_ODT_READ....................: 0x%08x\n"}, | |
248 {nvbct_lib_id_sdram_emc_zcal_ref_cnt, | |
249 " EMC_ZCAL_REF_CNT................: 0x%08x\n"}, | |
250 {nvbct_lib_id_sdram_emc_zcal_wait_cnt, | |
251 " EMC_ZCAL_WAIT_CNT...............: 0x%08x\n"}, | |
252 {nvbct_lib_id_sdram_emc_zcal_mrw_cmd, | |
253 " EMC_ZCAL_MRW_CMD................: 0x%08x\n"}, | |
254 {nvbct_lib_id_sdram_emc_mrs_reset_dll, | |
255 " EMC_MRS_RESET_DLL...............: 0x%08x\n"}, | |
256 {nvbct_lib_id_sdram_emc_mrw_zq_init_dev0, | |
257 " EMC_MRW_ZQ_INIT_DEV0............: 0x%08x\n"}, | |
258 {nvbct_lib_id_sdram_emc_mrw_zq_init_dev1, | |
259 " EMC_MRW_ZQ_INIT_DEV1............: 0x%08x\n"}, | |
260 {nvbct_lib_id_sdram_emc_mrw_zq_init_wait, | |
261 " EMC_MRW_ZQ_INIT_WAIT............: 0x%08x\n"}, | |
262 {nvbct_lib_id_sdram_emc_mrs_reset_dll_wait, | |
263 " EMC_MRS_RESET_DLL_WAIT..........: 0x%08x\n"}, | |
264 {nvbct_lib_id_sdram_emc_emrs_emr2, | |
265 " EMC_EMRS_EMR2...................: 0x%08x\n"}, | |
266 {nvbct_lib_id_sdram_emc_emrs_emr3, | |
267 " EMC_EMRS_EMR3...................: 0x%08x\n"}, | |
268 {nvbct_lib_id_sdram_emc_emrs_ddr2_dll_enable, | |
269 " EMC_EMRS_DDR2_DLL_ENABLE........: 0x%08x\n"}, | |
270 {nvbct_lib_id_sdram_emc_mrs_ddr2_dll_reset, | |
271 " EMC_MRS_DDR2_DLL_RESET..........: 0x%08x\n"}, | |
272 {nvbct_lib_id_sdram_emc_emrs_ddr2_ocd_calib, | |
273 " EMC_EMRS_DDR2_OCD_CALIB.........: 0x%08x\n"}, | |
274 {nvbct_lib_id_sdram_emc_ddr2_wait, | |
275 " EMC_DDR2_WAIT...................: 0x%08x\n"}, | |
276 {nvbct_lib_id_sdram_emc_cfg_clktrim0, | |
277 " EMC_CFG_CLKTRIM0................: 0x%08x\n"}, | |
278 {nvbct_lib_id_sdram_emc_cfg_clktrim1, | |
279 " EMC_CFG_CLKTRIM1................: 0x%08x\n"}, | |
280 {nvbct_lib_id_sdram_emc_cfg_clktrim2, | |
281 " EMC_CFG_CLKTRIM2................: 0x%08x\n"}, | |
282 {nvbct_lib_id_sdram_pmc_ddr_pwr, | |
283 " PMC_DDR_PWR.....................: 0x%08x\n"}, | |
284 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfga_pad_ctrl, | |
285 " APB_MISC_GP_XM2CFGA_PAD_CTRL....: 0x%08x\n"}, | |
286 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl, | |
287 " APB_MISC_GP_XM2CFGC_PAD_CTRL....: 0x%08x\n"}, | |
288 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl2, | |
289 " APB_MISC_GP_XM2CFGC_PAD_CTRL2...: 0x%08x\n"}, | |
290 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl, | |
291 " APB_MISC_GP_XM2CFGD_PAD_CTRL....: 0x%08x\n"}, | |
292 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl2, | |
293 " APB_MISC_GP_XM2CFGD_PAD_CTRL2...: 0x%08x\n"}, | |
294 {nvbct_lib_id_sdram_apb_misc_gp_xm2clkcfg_Pad_ctrl, | |
295 " APB_MISC_GP_XM2CLKCFG_PAD_CTRL..: 0x%08x\n"}, | |
296 {nvbct_lib_id_sdram_apb_misc_gp_xm2comp_pad_ctrl, | |
297 " APB_MISC_GP_XM2COMP_PAD_CTRL....: 0x%08x\n"}, | |
298 {nvbct_lib_id_sdram_apb_misc_gp_xm2vttgen_pad_ctrl, | |
299 " APB_MISC_GP_XM2VTTGEN_PAD_CTRL..: 0x%08x\n"}, | |
300 }; | |
301 | |
302 static const char *sdram_types[nvboot_memory_type_num] = { | 82 static const char *sdram_types[nvboot_memory_type_num] = { |
303 "None", "DDR", "LPDDR", "DDR2", "LPDDR2" | 83 "None", "DDR", "LPDDR", "DDR2", "LPDDR2" |
304 }; | 84 }; |
305 | 85 |
306 static void | 86 /*****************************************************************************/ |
307 usage(void) | 87 static void usage(void) |
308 { | 88 { |
309 printf("Usage: bct_dump bctfile\n"); | 89 printf("Usage: bct_dump bctfile\n"); |
310 printf(" bctfile BCT filename to read and display\n"); | 90 printf(" bctfile BCT filename to read and display\n"); |
311 } | 91 } |
| 92 /*****************************************************************************/ |
| 93 static int max_width(field_item const * table) |
| 94 { |
| 95 int width = 0; |
| 96 int i; |
312 | 97 |
313 int | 98 » for (i = 0; table[i].name != NULL; ++i) |
314 main(int argc, char *argv[]) | 99 » { |
| 100 » » int length = strlen(table[i].name); |
| 101 |
| 102 » » if (width < length) |
| 103 » » » width = length; |
| 104 » } |
| 105 |
| 106 » return width; |
| 107 } |
| 108 /*****************************************************************************/ |
| 109 static int display_field_value(field_item const * item, u_int32_t value) |
| 110 { |
| 111 » switch (item->type) |
| 112 » { |
| 113 » » case field_type_enum: |
| 114 » » » /* |
| 115 » » » * It would be ideal if we could take the enum value |
| 116 » » » * and programatically look up a string that the parse |
| 117 » » » * would accept for this field. The problem is that |
| 118 » » » * the mapping between field values and nvbct_lib_id |
| 119 » » » * values is hard coded in the nvbctlib source. For |
| 120 » » » * now we drop down to the u32 printing code. |
| 121 » » » * |
| 122 » » » * TODO(robotboy): Fix this |
| 123 » » » */ |
| 124 |
| 125 » » case field_type_u32: |
| 126 » » » printf("0x%08x", value); |
| 127 » » » break; |
| 128 |
| 129 » » case field_type_u8: |
| 130 » » » printf("0x%02x", value); |
| 131 » » » break; |
| 132 |
| 133 » » default: |
| 134 » » » printf("<UNKNOWN FIELD TYPE (%d)>", item->type); |
| 135 » » » return 1; |
| 136 » } |
| 137 |
| 138 » return 0; |
| 139 } |
| 140 /*****************************************************************************/ |
| 141 int main(int argc, char *argv[]) |
315 { | 142 { |
316 int e; | 143 int e; |
317 build_image_context context; | 144 build_image_context context; |
318 u_int32_t bootloaders_used; | 145 u_int32_t bootloaders_used; |
319 u_int32_t parameters_used; | 146 u_int32_t parameters_used; |
320 u_int32_t sdram_used; | 147 u_int32_t sdram_used; |
321 nvboot_dev_type type; | 148 nvboot_dev_type type; |
322 u_int32_t data; | 149 u_int32_t data; |
323 int i; | 150 int i; |
324 int j; | 151 int j; |
325 value_data const * device_values; | |
326 int device_count; | |
327 | 152 |
328 if (argc != 2) | 153 if (argc != 2) |
329 usage(); | 154 usage(); |
330 | 155 |
331 memset(&context, 0, sizeof(build_image_context)); | 156 memset(&context, 0, sizeof(build_image_context)); |
332 | 157 |
333 context.bct_filename = argv[1]; | 158 context.bct_filename = argv[1]; |
334 | 159 |
335 /* Set up the Nvbctlib function pointers. */ | 160 /* Set up the Nvbctlib function pointers. */ |
336 nvbct_lib_get_fns(&(context.bctlib)); | 161 nvbct_lib_get_fns(&(context.bctlib)); |
(...skipping 28 matching lines...) Expand all Loading... |
365 printf(bl_values[j].message, e == 0 ? data : -1); | 190 printf(bl_values[j].message, e == 0 ? data : -1); |
366 } | 191 } |
367 } | 192 } |
368 | 193 |
369 /* Display device values */ | 194 /* Display device values */ |
370 e = context.bctlib.get_value(nvbct_lib_id_num_param_sets, | 195 e = context.bctlib.get_value(nvbct_lib_id_num_param_sets, |
371 ¶meters_used, | 196 ¶meters_used, |
372 context.bct); | 197 context.bct); |
373 | 198 |
374 for (i = 0; (e == 0) && (i < parameters_used); ++i) { | 199 for (i = 0; (e == 0) && (i < parameters_used); ++i) { |
| 200 field_item const * device_field_table = NULL; |
| 201 field_item const * item; |
| 202 |
375 printf("DeviceParameter[%d]\n", i); | 203 printf("DeviceParameter[%d]\n", i); |
376 | 204 |
377 e = context.bctlib.getdev_param(i, | 205 e = context.bctlib.getdev_param(i, |
378 nvbct_lib_id_dev_type, | 206 nvbct_lib_id_dev_type, |
379 &type, | 207 &type, |
380 context.bct); | 208 context.bct); |
381 | 209 |
382 switch (type) | 210 switch (type) |
383 { | 211 { |
384 case nvboot_dev_type_spi: | 212 case nvboot_dev_type_spi: |
385 » » » » printf(" Type...........: SPI\n"); | 213 » » » » printf(" Type = SPI\n"); |
386 » » » » device_values = spi_values; | 214 » » » » device_field_table = s_spiflash_table; |
387 » » » » device_count = (sizeof(spi_values) / | |
388 » » » » » » sizeof(spi_values[0])); | |
389 break; | 215 break; |
390 | 216 |
391 case nvboot_dev_type_sdmmc: | 217 case nvboot_dev_type_sdmmc: |
392 » » » » printf(" Type...........: SDMMC\n"); | 218 » » » » printf(" Type = SDMMC\n"); |
393 » » » » device_values = sdmmc_values; | 219 » » » » device_field_table = s_sdmmc_table; |
394 » » » » device_count = (sizeof(sdmmc_values) / | 220 » » » » break; |
395 » » » » » » sizeof(sdmmc_values[0])); | 221 |
| 222 » » » case nvboot_dev_type_nand: |
| 223 » » » » printf(" Type = NAND\n"); |
| 224 » » » » device_field_table = s_nand_table; |
396 break; | 225 break; |
397 | 226 |
398 default: | 227 default: |
399 » » » » printf(" Type...........: Unknown (%d)\n", | 228 » » » » device_field_table = NULL; |
| 229 » » » » printf(" Type = <UNKNOWN TYPE (%d)>\n", |
400 type); | 230 type); |
401 device_values = NULL; | |
402 device_count = 0; | |
403 break; | 231 break; |
404 } | 232 } |
405 | 233 |
406 » » for (j = 0; j < device_count; ++j) { | 234 » » if (!device_field_table) |
407 » » » value_data» value = device_values[j]; | 235 » » » continue; |
408 | 236 |
| 237 int width = max_width(device_field_table); |
| 238 |
| 239 for (item = device_field_table; item->name != NULL; ++item) { |
409 e = context.bctlib.getdev_param(i, | 240 e = context.bctlib.getdev_param(i, |
410 » » » » » » » value.id, | 241 » » » » » » » item->enum_value, |
411 &data, | 242 &data, |
412 context.bct); | 243 context.bct); |
413 » » » printf(value.message, e == 0 ? data : -1); | 244 » » » printf(" %-*s = 0x%08x\n", |
| 245 » » » width, item->name, |
| 246 » » » e == 0 ? data : -1); |
414 } | 247 } |
415 } | 248 } |
416 | 249 |
417 /* Display SDRAM parameters sets */ | 250 /* Display SDRAM parameters sets */ |
418 e = context.bctlib.get_value(nvbct_lib_id_num_sdram_sets, | 251 e = context.bctlib.get_value(nvbct_lib_id_num_sdram_sets, |
419 &sdram_used, | 252 &sdram_used, |
420 context.bct); | 253 context.bct); |
421 | 254 |
422 for (i = 0; (e == 0) && (i < sdram_used); ++i) { | 255 for (i = 0; (e == 0) && (i < sdram_used); ++i) { |
423 printf("SDRAMParameter[%d]\n", i); | 256 printf("SDRAMParameter[%d]\n", i); |
424 | 257 |
425 e = context.bctlib.get_sdram_params(i, | 258 e = context.bctlib.get_sdram_params(i, |
426 nvbct_lib_id_sdram_memory_type, | 259 nvbct_lib_id_sdram_memory_type, |
427 &type, | 260 &type, |
428 context.bct); | 261 context.bct); |
429 | 262 |
430 printf(" Type............................: %s\n", | 263 printf(" Type............................: %s\n", |
431 type < nvboot_memory_type_num ? sdram_types[type] | 264 type < nvboot_memory_type_num ? sdram_types[type] |
432 : "Unknown"); | 265 : "Unknown"); |
433 | 266 |
434 » » for (j = 0; j < sizeof(sdram_values) / sizeof(sdram_values[0]); | 267 » » int width = max_width(s_sdram_field_table); |
435 » » ++j) { | 268 » » field_item const * item; |
| 269 |
| 270 » » for (item = s_sdram_field_table; item->name != NULL; ++item) { |
436 e = context.bctlib.get_sdram_params(i, | 271 e = context.bctlib.get_sdram_params(i, |
437 » » » » » » sdram_values[j].id, | 272 » » » » » » » item->enum_value, |
438 » » » » » » &data, | 273 » » » » » » » &data, |
439 » » » » » » context.bct); | 274 » » » » » » » context.bct); |
440 » » » printf(sdram_values[j].message, e == 0 ? data : -1); | 275 » » » printf(" %-*s = ", width, item->name); |
| 276 |
| 277 » » » if (e != 0) |
| 278 » » » » printf("<ERROR reading parameter (%d)>", e); |
| 279 » » » else |
| 280 » » » » display_field_value(item, data); |
| 281 |
| 282 » » » printf("\n"); |
441 } | 283 } |
442 } | 284 } |
443 | 285 |
444 /* Clean up memory. */ | 286 /* Clean up memory. */ |
445 cleanup_context(&context); | 287 cleanup_context(&context); |
446 | 288 |
447 return e; | 289 return e; |
448 } | 290 } |
OLD | NEW |