spi: Tegra2: increase SPI FLASH clock to 24MHz

drivers/spi/tegra2_spi.c

Index: drivers/spi/tegra2_spi.c
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
index 177bc71b0d148825131f8f231cd1365de5d6d51c..0d9512d1a2a01951fc6e5015f67eaccd14b139ec 100755
--- a/drivers/spi/tegra2_spi.c
+++ b/drivers/spi/tegra2_spi.c
@@ -91,9 +91,11 @@ void spi_init(void)
 	NV_CLK_RST_WRITE(0x14, (val | 0x800));
 	debug("spi_init: ClkEnable = %08x\n", val);
 
-	/* Change default SPI clock from 12MHz to 6MHz, same as BootROM */
+	/* Change SPI clock to 24MHz */
 	NV_CLK_RST_READ(0x114, val);
-	NV_CLK_RST_WRITE(0x114, (val | 0x2));
+	val &= 0x0FFFFFF0;		/* src = PLLP_OUT0 */
+	val |= ((9-1) << 1);		/* div = 9 in 7.1 format */

[robotboy, 2011/03/31 18:32:56]

I'm a little confused by this.  It looks like you're masking off the top and
bottom nibble of val and then setting the bottom bit of the second to bottom
nibble (the bottom nibble that was left alone by the mask).  And the comment
seems to indicate that the divisor is an 8 bit quantity (7.1 fixed point I
assume).  So it seems like the mask above would leave half of the divisor alone.
 I haven't hit the TRM to check the register layout yet.

[robotboy, 2011/03/31 18:39:47]

After consulting the TRM, I think what you want here is:

val &= 0x3fffff00;

-Anton

[Tom Warren, 2011/03/31 19:17:32]

Doh! You're right. Worked OK since there was never a divider set that was >8 (by
BootROM or BCT or my old code).

I'll fix & resubmit. Thanks.

+	NV_CLK_RST_WRITE(0x114, val);
 	debug("spi_init: ClkSrc = %08x\n", val);
 
 	NV_CLK_RST_READ(0x08, val);