spi: Tegra2: increase SPI FLASH clock to 24MHz

drivers/spi/tegra2_spi.c

 /*
  * Copyright (c) 2010 NVIDIA Corporation
  * With help from the mpc8xxx SPI driver
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ skipping 73 matching lines @@
          * SPI reset/clocks init - reset SPI, set clocks, release from reset
          */
         NV_CLK_RST_READ(0x08, val);
         NV_CLK_RST_WRITE(0x08, (val | 0x800));
         debug("spi_init: ClkRst = %08x\n", val);
 
         NV_CLK_RST_READ(0x14, val);
         NV_CLK_RST_WRITE(0x14, (val | 0x800));
         debug("spi_init: ClkEnable = %08x\n", val);
 
-        /* Change default SPI clock from 12MHz to 6MHz, same as BootROM */
+        /* Change SPI clock to 24MHz */
         NV_CLK_RST_READ(0x114, val);
-        NV_CLK_RST_WRITE(0x114, (val | 0x2));
+        val &= 0x3FFFFF00;              /* src = PLLP_OUT0 */
+        val |= ((9-1) << 1);            /* div = 9 in 7.1 format */
+        NV_CLK_RST_WRITE(0x114, val);
         debug("spi_init: ClkSrc = %08x\n", val);
 
         NV_CLK_RST_READ(0x08, val);
         NV_CLK_RST_WRITE(0x08, (val & 0xFFFFF7FF));
         debug("spi_init: ClkRst final = %08x\n", val);
 
         /* Clear stale status here */
 
         spi->status = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
                 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
@@ skipping 224 matching lines @@
                 spi->status = status;                   /* ACK RDY, etc. bits */
         }
 
         if (flags & SPI_XFER_END)
                 spi_cs_deactivate(slave);
 
         debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
          tmpdin, status);
         return ret;
 }