| OLD | NEW |
| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
| (...skipping 734 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 745 } | 745 } |
| 746 } | 746 } |
| 747 | 747 |
| 748 | 748 |
| 749 void LCodeGen::DoUnknownOSRValue(LUnknownOSRValue* instr) { | 749 void LCodeGen::DoUnknownOSRValue(LUnknownOSRValue* instr) { |
| 750 // Nothing to do. | 750 // Nothing to do. |
| 751 } | 751 } |
| 752 | 752 |
| 753 | 753 |
| 754 void LCodeGen::DoModI(LModI* instr) { | 754 void LCodeGen::DoModI(LModI* instr) { |
| 755 LOperand* right = instr->InputAt(1); | 755 if (HMod::cast(instr->hydrogen())->HasPowerOf2Divisor()) { |
| 756 ASSERT(ToRegister(instr->result()).is(rdx)); | 756 Register dividend = ToRegister(instr->InputAt(0)); |
| 757 ASSERT(ToRegister(instr->InputAt(0)).is(rax)); | |
| 758 ASSERT(!ToRegister(instr->InputAt(1)).is(rax)); | |
| 759 ASSERT(!ToRegister(instr->InputAt(1)).is(rdx)); | |
| 760 | 757 |
| 761 Register right_reg = ToRegister(right); | 758 int32_t divisor = |
| 759 HConstant::cast( |
| 760 HMod::cast(instr->hydrogen())->right())->Integer32Value(); |
| 762 | 761 |
| 763 // Check for x % 0. | 762 if (divisor < 0) divisor = -divisor; |
| 764 if (instr->hydrogen()->CheckFlag(HValue::kCanBeDivByZero)) { | |
| 765 __ testl(right_reg, right_reg); | |
| 766 DeoptimizeIf(zero, instr->environment()); | |
| 767 } | |
| 768 | 763 |
| 769 // Sign extend eax to edx. (We are using only the low 32 bits of the values.) | 764 NearLabel positive_dividend, done; |
| 770 __ cdq(); | 765 __ testl(dividend, dividend); |
| 771 | 766 __ j(not_sign, &positive_dividend); |
| 772 // Check for (0 % -x) that will produce negative zero. | 767 __ negl(dividend); |
| 773 if (instr->hydrogen()->CheckFlag(HValue::kBailoutOnMinusZero)) { | 768 __ andl(dividend, Immediate(divisor - 1)); |
| 774 NearLabel positive_left; | 769 __ negl(dividend); |
| 775 NearLabel done; | 770 if (instr->hydrogen()->CheckFlag(HValue::kBailoutOnMinusZero)) { |
| 776 __ testl(rax, rax); | 771 __ j(not_zero, &done); |
| 777 __ j(not_sign, &positive_left); | 772 DeoptimizeIf(no_condition, instr->environment()); |
| 778 __ idivl(right_reg); | 773 } |
| 779 | 774 __ bind(&positive_dividend); |
| 780 // Test the remainder for 0, because then the result would be -0. | 775 __ andl(dividend, Immediate(divisor - 1)); |
| 781 __ testl(rdx, rdx); | |
| 782 __ j(not_zero, &done); | |
| 783 | |
| 784 DeoptimizeIf(no_condition, instr->environment()); | |
| 785 __ bind(&positive_left); | |
| 786 __ idivl(right_reg); | |
| 787 __ bind(&done); | 776 __ bind(&done); |
| 788 } else { | 777 } else { |
| 789 __ idivl(right_reg); | 778 LOperand* right = instr->InputAt(1); |
| 779 Register right_reg = ToRegister(right); |
| 780 |
| 781 ASSERT(ToRegister(instr->result()).is(rdx)); |
| 782 ASSERT(ToRegister(instr->InputAt(0)).is(rax)); |
| 783 ASSERT(!right_reg.is(rax)); |
| 784 ASSERT(!right_reg.is(rdx)); |
| 785 |
| 786 // Check for x % 0. |
| 787 if (instr->hydrogen()->CheckFlag(HValue::kCanBeDivByZero)) { |
| 788 __ testl(right_reg, right_reg); |
| 789 DeoptimizeIf(zero, instr->environment()); |
| 790 } |
| 791 |
| 792 // Sign extend eax to edx. (We are using only the low 32 bits of the values.
) |
| 793 __ cdq(); |
| 794 |
| 795 // Check for (0 % -x) that will produce negative zero. |
| 796 if (instr->hydrogen()->CheckFlag(HValue::kBailoutOnMinusZero)) { |
| 797 NearLabel positive_left; |
| 798 NearLabel done; |
| 799 __ testl(rax, rax); |
| 800 __ j(not_sign, &positive_left); |
| 801 __ idivl(right_reg); |
| 802 |
| 803 // Test the remainder for 0, because then the result would be -0. |
| 804 __ testl(rdx, rdx); |
| 805 __ j(not_zero, &done); |
| 806 |
| 807 DeoptimizeIf(no_condition, instr->environment()); |
| 808 __ bind(&positive_left); |
| 809 __ idivl(right_reg); |
| 810 __ bind(&done); |
| 811 } else { |
| 812 __ idivl(right_reg); |
| 813 } |
| 790 } | 814 } |
| 791 } | 815 } |
| 792 | 816 |
| 793 | 817 |
| 794 void LCodeGen::DoDivI(LDivI* instr) { | 818 void LCodeGen::DoDivI(LDivI* instr) { |
| 795 LOperand* right = instr->InputAt(1); | 819 LOperand* right = instr->InputAt(1); |
| 796 ASSERT(ToRegister(instr->result()).is(rax)); | 820 ASSERT(ToRegister(instr->result()).is(rax)); |
| 797 ASSERT(ToRegister(instr->InputAt(0)).is(rax)); | 821 ASSERT(ToRegister(instr->InputAt(0)).is(rax)); |
| 798 ASSERT(!ToRegister(instr->InputAt(1)).is(rax)); | 822 ASSERT(!ToRegister(instr->InputAt(1)).is(rax)); |
| 799 ASSERT(!ToRegister(instr->InputAt(1)).is(rdx)); | 823 ASSERT(!ToRegister(instr->InputAt(1)).is(rdx)); |
| (...skipping 2891 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3691 RegisterEnvironmentForDeoptimization(environment); | 3715 RegisterEnvironmentForDeoptimization(environment); |
| 3692 ASSERT(osr_pc_offset_ == -1); | 3716 ASSERT(osr_pc_offset_ == -1); |
| 3693 osr_pc_offset_ = masm()->pc_offset(); | 3717 osr_pc_offset_ = masm()->pc_offset(); |
| 3694 } | 3718 } |
| 3695 | 3719 |
| 3696 #undef __ | 3720 #undef __ |
| 3697 | 3721 |
| 3698 } } // namespace v8::internal | 3722 } } // namespace v8::internal |
| 3699 | 3723 |
| 3700 #endif // V8_TARGET_ARCH_X64 | 3724 #endif // V8_TARGET_ARCH_X64 |
| OLD | NEW |