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Side by Side Diff: src/arm/assembler-arm.h

Issue 6661022: ARM: Port r7089 to ARM... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 9 years, 9 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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382 // rm <shift_op> shift_imm 382 // rm <shift_op> shift_imm
383 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); 383 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
384 384
385 // rm <shift_op> rs 385 // rm <shift_op> rs
386 explicit Operand(Register rm, ShiftOp shift_op, Register rs); 386 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
387 387
388 // Return true if this is a register operand. 388 // Return true if this is a register operand.
389 INLINE(bool is_reg() const); 389 INLINE(bool is_reg() const);
390 390
391 // Return true if this operand fits in one instruction so that no 391 // Return true if this operand fits in one instruction so that no
392 // 2-instruction solution with a load into the ip register is necessary. 392 // 2-instruction solution with a load into the ip register is necessary. If
393 bool is_single_instruction() const; 393 // the instruction this operand is used for is a MOV or MVN instruction the
394 // actual instruction to use is required for this calculation. For other
395 // instructions instr is ignored.
396 bool is_single_instruction(Instr instr = 0) const;
394 bool must_use_constant_pool() const; 397 bool must_use_constant_pool() const;
395 398
396 inline int32_t immediate() const { 399 inline int32_t immediate() const {
397 ASSERT(!rm_.is_valid()); 400 ASSERT(!rm_.is_valid());
398 return imm32_; 401 return imm32_;
399 } 402 }
400 403
401 Register rm() const { return rm_; } 404 Register rm() const { return rm_; }
402 Register rs() const { return rs_; } 405 Register rs() const { return rs_; }
403 ShiftOp shift_op() const { return shift_op_; } 406 ShiftOp shift_op() const { return shift_op_; }
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1285 public: 1288 public:
1286 explicit EnsureSpace(Assembler* assembler) { 1289 explicit EnsureSpace(Assembler* assembler) {
1287 assembler->CheckBuffer(); 1290 assembler->CheckBuffer();
1288 } 1291 }
1289 }; 1292 };
1290 1293
1291 1294
1292 } } // namespace v8::internal 1295 } } // namespace v8::internal
1293 1296
1294 #endif // V8_ARM_ASSEMBLER_ARM_H_ 1297 #endif // V8_ARM_ASSEMBLER_ARM_H_
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