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1 /* | 1 /* |
2 * drivers/video/tegra/dc/hdmi.c | 2 * drivers/video/tegra/dc/hdmi.c |
3 * | 3 * |
4 * Copyright (C) 2010 Google, Inc. | 4 * Copyright (C) 2010 Google, Inc. |
5 * Author: Erik Gilling <konkers@android.com> | 5 * Author: Erik Gilling <konkers@android.com> |
6 * | 6 * |
7 * This software is licensed under the terms of the GNU General Public | 7 * This software is licensed under the terms of the GNU General Public |
8 * License version 2, as published by the Free Software Foundation, and | 8 * License version 2, as published by the Free Software Foundation, and |
9 * may be copied, distributed, and modified under those terms. | 9 * may be copied, distributed, and modified under those terms. |
10 * | 10 * |
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678 else | 678 else |
679 delta = 9; | 679 delta = 9; |
680 | 680 |
681 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); | 681 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); |
682 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) | | 682 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) | |
683 AUDIO_FS_HIGH(eight_half + delta), | 683 AUDIO_FS_HIGH(eight_half + delta), |
684 HDMI_NV_PDISP_AUDIO_FS(i)); | 684 HDMI_NV_PDISP_AUDIO_FS(i)); |
685 } | 685 } |
686 } | 686 } |
687 | 687 |
688 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc) | 688 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq) |
689 { | 689 { |
690 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc); | 690 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc); |
691 const struct tegra_hdmi_audio_config *config; | 691 const struct tegra_hdmi_audio_config *config; |
692 unsigned long audio_n; | 692 unsigned long audio_n; |
693 unsigned audio_freq = 44100; /* TODO: find some way of configuring this
*/ | |
694 | 693 |
695 tegra_hdmi_writel(hdmi, | 694 tegra_hdmi_writel(hdmi, |
696 AUDIO_CNTRL0_ERROR_TOLERANCE(6) | | 695 AUDIO_CNTRL0_ERROR_TOLERANCE(6) | |
697 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) | | 696 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) | |
698 AUDIO_CNTRL0_SOURCE_SELECT_AUTO, | 697 AUDIO_CNTRL0_SOURCE_SELECT_AUTO, |
699 HDMI_NV_PDISP_AUDIO_CNTRL0); | 698 HDMI_NV_PDISP_AUDIO_CNTRL0); |
700 | 699 |
701 config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk); | 700 config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk); |
702 if (!config) { | 701 if (!config) { |
703 dev_err(&dc->ndev->dev, | 702 dev_err(&dc->ndev->dev, |
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723 HDMI_NV_PDISP_HDMI_SPARE); | 722 HDMI_NV_PDISP_HDMI_SPARE); |
724 | 723 |
725 audio_n &= ~AUDIO_N_RESETF; | 724 audio_n &= ~AUDIO_N_RESETF; |
726 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N); | 725 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N); |
727 | 726 |
728 tegra_dc_hdmi_setup_audio_fs_tables(dc); | 727 tegra_dc_hdmi_setup_audio_fs_tables(dc); |
729 | 728 |
730 return 0; | 729 return 0; |
731 } | 730 } |
732 | 731 |
| 732 int tegra_dc_hdmi_set_audio_sample_rate(unsigned audio_freq) |
| 733 { |
| 734 int i, ret; |
| 735 struct tegra_dc *dc; |
| 736 struct tegra_dc_hdmi_data *hdmi; |
| 737 |
| 738 for (i = 0; i < TEGRA_MAX_DC; i++) { |
| 739 dc = tegra_dc_get_dc(i); |
| 740 if (!dc) |
| 741 continue; |
| 742 hdmi = tegra_dc_get_outdata(dc); |
| 743 if (!hdmi) |
| 744 continue; |
| 745 ret = tegra_dc_hdmi_setup_audio(dc, audio_freq); |
| 746 if (ret) |
| 747 return ret; |
| 748 } |
| 749 |
| 750 return 0; |
| 751 } |
| 752 EXPORT_SYMBOL(tegra_dc_hdmi_set_audio_sample_rate); |
| 753 |
733 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg, | 754 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg, |
734 u8 type, u8 version, void *data, int le
n) | 755 u8 type, u8 version, void *data, int le
n) |
735 { | 756 { |
736 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc); | 757 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc); |
737 u32 subpack[2]; /* extra byte for zero padding of subpack */ | 758 u32 subpack[2]; /* extra byte for zero padding of subpack */ |
738 int i; | 759 int i; |
739 u8 csum; | 760 u8 csum; |
740 | 761 |
741 /* first byte of data is the checksum */ | 762 /* first byte of data is the checksum */ |
742 csum = type + version + len - 1; | 763 csum = type + version + len - 1; |
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930 | 951 |
931 clk_disable(hdmi->disp1_clk); | 952 clk_disable(hdmi->disp1_clk); |
932 clk_disable(hdmi->disp2_clk); | 953 clk_disable(hdmi->disp2_clk); |
933 | 954 |
934 dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4; | 955 dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4; |
935 tegra_hdmi_writel(hdmi, | 956 tegra_hdmi_writel(hdmi, |
936 SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) | | 957 SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) | |
937 SOR_REFCLK_DIV_FRAC(dispclk_div_8_2), | 958 SOR_REFCLK_DIV_FRAC(dispclk_div_8_2), |
938 HDMI_NV_PDISP_SOR_REFCLK); | 959 HDMI_NV_PDISP_SOR_REFCLK); |
939 | 960 |
940 » err = tegra_dc_hdmi_setup_audio(dc); | 961 » err = tegra_dc_hdmi_setup_audio(dc, 44100); |
941 if (err < 0) | 962 if (err < 0) |
942 dvi = true; | 963 dvi = true; |
943 | 964 |
944 rekey = HDMI_REKEY_DEFAULT; | 965 rekey = HDMI_REKEY_DEFAULT; |
945 val = HDMI_CTRL_REKEY(rekey); | 966 val = HDMI_CTRL_REKEY(rekey); |
946 val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width + | 967 val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width + |
947 dc->mode.h_back_porch + | 968 dc->mode.h_back_porch + |
948 dc->mode.h_front_porch - | 969 dc->mode.h_front_porch - |
949 rekey - 18) / 32); | 970 rekey - 18) / 32); |
950 if (!dvi) | 971 if (!dvi) |
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1100 struct tegra_dc_out_ops tegra_dc_hdmi_ops = { | 1121 struct tegra_dc_out_ops tegra_dc_hdmi_ops = { |
1101 .init = tegra_dc_hdmi_init, | 1122 .init = tegra_dc_hdmi_init, |
1102 .destroy = tegra_dc_hdmi_destroy, | 1123 .destroy = tegra_dc_hdmi_destroy, |
1103 .enable = tegra_dc_hdmi_enable, | 1124 .enable = tegra_dc_hdmi_enable, |
1104 .disable = tegra_dc_hdmi_disable, | 1125 .disable = tegra_dc_hdmi_disable, |
1105 .detect = tegra_dc_hdmi_detect, | 1126 .detect = tegra_dc_hdmi_detect, |
1106 .suspend = tegra_dc_hdmi_suspend, | 1127 .suspend = tegra_dc_hdmi_suspend, |
1107 .resume = tegra_dc_hdmi_resume, | 1128 .resume = tegra_dc_hdmi_resume, |
1108 }; | 1129 }; |
1109 | 1130 |
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