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Issue 6626016: Add support for SDRAM registers printing to bct_dump. (Closed)
Patch Set: Rebase against master Created 9 years, 9 months ago
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1 /** 1 /**
2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
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89 89
90 static value_data const sdmmc_values[] = { 90 static value_data const sdmmc_values[] = {
91 {nvbct_lib_id_sdmmc_clock_divider, 91 {nvbct_lib_id_sdmmc_clock_divider,
92 " Clock divider..: %d\n"}, 92 " Clock divider..: %d\n"},
93 {nvbct_lib_id_sdmmc_data_width, 93 {nvbct_lib_id_sdmmc_data_width,
94 " Data width.....: %d\n"}, 94 " Data width.....: %d\n"},
95 {nvbct_lib_id_sdmmc_max_power_class_supported, 95 {nvbct_lib_id_sdmmc_max_power_class_supported,
96 " Power class....: %d\n"}, 96 " Power class....: %d\n"},
97 }; 97 };
98 98
99 static value_data const sdram_values[] = {
100 {nvbct_lib_id_sdram_pllm_charge_pump_setup_ctrl,
101 " PLLM_CHARGE_PUMP_SETUP_CTRL.....: 0x%08x\n"},
102 {nvbct_lib_id_sdram_pllm_loop_filter_setup_ctrl,
103 " PLLM_LOOP_FILTER_SETUP_CTRL.....: 0x%08x\n"},
104 {nvbct_lib_id_sdram_pllm_input_divider,
105 " PLLM_INPUT_DIVIDER..............: 0x%08x\n"},
106 {nvbct_lib_id_sdram_pllm_feedback_divider,
107 " PLLM_FEEDBACK_DIVIDER...........: 0x%08x\n"},
108 {nvbct_lib_id_sdram_pllm_post_divider,
109 " PLLM_POST_DIVIDER...............: 0x%08x\n"},
110 {nvbct_lib_id_sdram_pllm_stable_time,
111 " PLLM_STABLE_TIME................: 0x%08x\n"},
112 {nvbct_lib_id_sdram_emc_clock_divider,
113 " EMC_CLOCK_DIVIDER...............: 0x%08x\n"},
114 {nvbct_lib_id_sdram_emc_auto_cal_interval,
115 " EMC_AUTO_CAL_INTERVAL...........: 0x%08x\n"},
116 {nvbct_lib_id_sdram_emc_auto_cal_config,
117 " EMC_AUTO_CAL_CONFIG.............: 0x%08x\n"},
118 {nvbct_lib_id_sdram_emc_auto_cal_wait,
119 " EMC_AUTO_CAL_WAIT...............: 0x%08x\n"},
120 {nvbct_lib_id_sdram_emc_pin_program_wait,
121 " EMC_PIN_PROGRAM_WAIT............: 0x%08x\n"},
122 {nvbct_lib_id_sdram_emc_rc,
123 " EMC_RC..........................: 0x%08x\n"},
124 {nvbct_lib_id_sdram_emc_rfc,
125 " EMC_RFC.........................: 0x%08x\n"},
126 {nvbct_lib_id_sdram_emc_ras,
127 " EMC_RAS.........................: 0x%08x\n"},
128 {nvbct_lib_id_sdram_emc_rp,
129 " EMC_RP..........................: 0x%08x\n"},
130 {nvbct_lib_id_sdram_emc_r2w,
131 " EMC_R2W.........................: 0x%08x\n"},
132 {nvbct_lib_id_sdram_emc_w2r,
133 " EMC_W2R.........................: 0x%08x\n"},
134 {nvbct_lib_id_sdram_emc_r2p,
135 " EMC_R2P.........................: 0x%08x\n"},
136 {nvbct_lib_id_sdram_emc_w2p,
137 " EMC_W2P.........................: 0x%08x\n"},
138 {nvbct_lib_id_sdram_emc_rd_rcd,
139 " EMC_RD_RCD......................: 0x%08x\n"},
140 {nvbct_lib_id_sdram_emc_wr_rcd,
141 " EMC_WR_RCD......................: 0x%08x\n"},
142 {nvbct_lib_id_sdram_emc_rrd,
143 " EMC_RRD.........................: 0x%08x\n"},
144 {nvbct_lib_id_sdram_emc_rext,
145 " EMC_REXT........................: 0x%08x\n"},
146 {nvbct_lib_id_sdram_emc_wdv,
147 " EMC_WDV.........................: 0x%08x\n"},
148 {nvbct_lib_id_sdram_emc_quse,
149 " EMC_QUSE........................: 0x%08x\n"},
150 {nvbct_lib_id_sdram_emc_qrst,
151 " EMC_QRST........................: 0x%08x\n"},
152 {nvbct_lib_id_sdram_emc_qsafe,
153 " EMC_QSAFE.......................: 0x%08x\n"},
154 {nvbct_lib_id_sdram_emc_rdv,
155 " EMC_RDV.........................: 0x%08x\n"},
156 {nvbct_lib_id_sdram_emc_refresh,
157 " EMC_REFRESH.....................: 0x%08x\n"},
158 {nvbct_lib_id_sdram_emc_burst_refresh_num,
159 " EMC_BURST_REFRESH_NUM...........: 0x%08x\n"},
160 {nvbct_lib_id_sdram_emc_pdex2wr,
161 " EMC_PDEX2WR.....................: 0x%08x\n"},
162 {nvbct_lib_id_sdram_emc_pdex2rd,
163 " EMC_PDEX2RD.....................: 0x%08x\n"},
164 {nvbct_lib_id_sdram_emc_pchg2pden,
165 " EMC_PCHG2PDEN...................: 0x%08x\n"},
166 {nvbct_lib_id_sdram_emc_act2pden,
167 " EMC_ACT2PDEN....................: 0x%08x\n"},
168 {nvbct_lib_id_sdram_emc_ar2pden,
169 " EMC_AR2PDEN.....................: 0x%08x\n"},
170 {nvbct_lib_id_sdram_emc_rw2pden,
171 " EMC_RW2PDEN.....................: 0x%08x\n"},
172 {nvbct_lib_id_sdram_emc_txsr,
173 " EMC_TXSR........................: 0x%08x\n"},
174 {nvbct_lib_id_sdram_emc_tcke,
175 " EMC_TCKE........................: 0x%08x\n"},
176 {nvbct_lib_id_sdram_emc_tfaw,
177 " EMC_TFAW........................: 0x%08x\n"},
178 {nvbct_lib_id_sdram_emc_trpab,
179 " EMC_TRPAB.......................: 0x%08x\n"},
180 {nvbct_lib_id_sdram_emc_tclkstable,
181 " EMC_TCLKSTABLE..................: 0x%08x\n"},
182 {nvbct_lib_id_sdram_emc_tclkstop,
183 " EMC_TCLKSTOP....................: 0x%08x\n"},
184 {nvbct_lib_id_sdram_emc_trefbw,
185 " EMC_TREFBW......................: 0x%08x\n"},
186 {nvbct_lib_id_sdram_emc_quse_extra,
187 " EMC_QUSE_EXTRA..................: 0x%08x\n"},
188 {nvbct_lib_id_sdram_emc_fbio_cfg1,
189 " EMC_FBIO_CFG1...................: 0x%08x\n"},
190 {nvbct_lib_id_sdram_emc_fbio_dqsib_dly,
191 " EMC_FBIO_DQSIB_DLY..............: 0x%08x\n"},
192 {nvbct_lib_id_sdram_emc_fbio_dqsib_dly_msb,
193 " EMC_FBIO_DQSIB_DLY_MSB..........: 0x%08x\n"},
194 {nvbct_lib_id_sdram_emc_fbio_quse_dly,
195 " EMC_FBIO_QUSE_DLY...............: 0x%08x\n"},
196 {nvbct_lib_id_sdram_emc_fbio_quse_dly_msb,
197 " EMC_FBIO_QUSE_DLY_MSB...........: 0x%08x\n"},
198 {nvbct_lib_id_sdram_emc_fbio_cfg5,
199 " EMC_FBIO_CFG5...................: 0x%08x\n"},
200 {nvbct_lib_id_sdram_emc_fbio_cfg6,
201 " EMC_FBIO_CFG6...................: 0x%08x\n"},
202 {nvbct_lib_id_sdram_emc_fbio_spare,
203 " EMC_FBIO_SPARE..................: 0x%08x\n"},
204 {nvbct_lib_id_sdram_emc_mrs,
205 " EMC_MRS.........................: 0x%08x\n"},
206 {nvbct_lib_id_sdram_emc_emrs,
207 " EMC_EMRS........................: 0x%08x\n"},
208 {nvbct_lib_id_sdram_emc_mrw1,
209 " EMC_MRW1........................: 0x%08x\n"},
210 {nvbct_lib_id_sdram_emc_mrw2,
211 " EMC_MRW2........................: 0x%08x\n"},
212 {nvbct_lib_id_sdram_emc_mrw3,
213 " EMC_MRW3........................: 0x%08x\n"},
214 {nvbct_lib_id_sdram_emc_mrw_reset_command,
215 " EMC_MRW_RESET_COMMAND...........: 0x%08x\n"},
216 {nvbct_lib_id_sdram_emc_mrw_reset_ninit_wait,
217 " EMC_MRW_RESET_NINIT_WAIT........: 0x%08x\n"},
218 {nvbct_lib_id_sdram_emc_adr_cfg,
219 " EMC_ADR_CFG.....................: 0x%08x\n"},
220 {nvbct_lib_id_sdram_emc_adr_cfg1,
221 " EMC_ADR_CFG1....................: 0x%08x\n"},
222 {nvbct_lib_id_sdram_mc_emem_Cfg,
223 " MC_EMEM_CFG.....................: 0x%08x\n"},
224 {nvbct_lib_id_sdram_mc_lowlatency_config,
225 " MC_LOWLATENCY_CONFIG............: 0x%08x\n"},
226 {nvbct_lib_id_sdram_emc_cfg,
227 " EMC_CFG.........................: 0x%08x\n"},
228 {nvbct_lib_id_sdram_emc_cfg2,
229 " EMC_CFG2........................: 0x%08x\n"},
230 {nvbct_lib_id_sdram_emc_dbg,
231 " EMC_DBG.........................: 0x%08x\n"},
232 {nvbct_lib_id_sdram_ahb_arbitration_xbar_ctrl,
233 " AHB_ARBITRATION_XBAR_CTRL.......: 0x%08x\n"},
234 {nvbct_lib_id_sdram_emc_cfg_dig_dll,
235 " EMC_CFG_DIG_DLL.................: 0x%08x\n"},
236 {nvbct_lib_id_sdram_emc_dll_xform_dqs,
237 " EMC_DLL_XFORM_DQS...............: 0x%08x\n"},
238 {nvbct_lib_id_sdram_emc_dll_xform_quse,
239 " EMC_DLL_XFORM_QUSE..............: 0x%08x\n"},
240 {nvbct_lib_id_sdram_warm_boot_wait,
241 " WARM_BOOT_WAIT..................: 0x%08x\n"},
242 {nvbct_lib_id_sdram_emc_ctt_term_ctrl,
243 " EMC_CTT_TERM_CTRL...............: 0x%08x\n"},
244 {nvbct_lib_id_sdram_emc_odt_write,
245 " EMC_ODT_WRITE...................: 0x%08x\n"},
246 {nvbct_lib_id_sdram_emc_odt_read,
247 " EMC_ODT_READ....................: 0x%08x\n"},
248 {nvbct_lib_id_sdram_emc_zcal_ref_cnt,
249 " EMC_ZCAL_REF_CNT................: 0x%08x\n"},
250 {nvbct_lib_id_sdram_emc_zcal_wait_cnt,
251 " EMC_ZCAL_WAIT_CNT...............: 0x%08x\n"},
252 {nvbct_lib_id_sdram_emc_zcal_mrw_cmd,
253 " EMC_ZCAL_MRW_CMD................: 0x%08x\n"},
254 {nvbct_lib_id_sdram_emc_mrs_reset_dll,
255 " EMC_MRS_RESET_DLL...............: 0x%08x\n"},
256 {nvbct_lib_id_sdram_emc_mrw_zq_init_dev0,
257 " EMC_MRW_ZQ_INIT_DEV0............: 0x%08x\n"},
258 {nvbct_lib_id_sdram_emc_mrw_zq_init_dev1,
259 " EMC_MRW_ZQ_INIT_DEV1............: 0x%08x\n"},
260 {nvbct_lib_id_sdram_emc_mrw_zq_init_wait,
261 " EMC_MRW_ZQ_INIT_WAIT............: 0x%08x\n"},
262 {nvbct_lib_id_sdram_emc_mrs_reset_dll_wait,
263 " EMC_MRS_RESET_DLL_WAIT..........: 0x%08x\n"},
264 {nvbct_lib_id_sdram_emc_emrs_emr2,
265 " EMC_EMRS_EMR2...................: 0x%08x\n"},
266 {nvbct_lib_id_sdram_emc_emrs_emr3,
267 " EMC_EMRS_EMR3...................: 0x%08x\n"},
268 {nvbct_lib_id_sdram_emc_emrs_ddr2_dll_enable,
269 " EMC_EMRS_DDR2_DLL_ENABLE........: 0x%08x\n"},
270 {nvbct_lib_id_sdram_emc_mrs_ddr2_dll_reset,
271 " EMC_MRS_DDR2_DLL_RESET..........: 0x%08x\n"},
272 {nvbct_lib_id_sdram_emc_emrs_ddr2_ocd_calib,
273 " EMC_EMRS_DDR2_OCD_CALIB.........: 0x%08x\n"},
274 {nvbct_lib_id_sdram_emc_ddr2_wait,
275 " EMC_DDR2_WAIT...................: 0x%08x\n"},
276 {nvbct_lib_id_sdram_emc_cfg_clktrim0,
277 " EMC_CFG_CLKTRIM0................: 0x%08x\n"},
278 {nvbct_lib_id_sdram_emc_cfg_clktrim1,
279 " EMC_CFG_CLKTRIM1................: 0x%08x\n"},
280 {nvbct_lib_id_sdram_emc_cfg_clktrim2,
281 " EMC_CFG_CLKTRIM2................: 0x%08x\n"},
282 {nvbct_lib_id_sdram_pmc_ddr_pwr,
283 " PMC_DDR_PWR.....................: 0x%08x\n"},
284 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfga_pad_ctrl,
285 " APB_MISC_GP_XM2CFGA_PAD_CTRL....: 0x%08x\n"},
286 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl,
287 " APB_MISC_GP_XM2CFGC_PAD_CTRL....: 0x%08x\n"},
288 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl2,
289 " APB_MISC_GP_XM2CFGC_PAD_CTRL2...: 0x%08x\n"},
290 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl,
291 " APB_MISC_GP_XM2CFGD_PAD_CTRL....: 0x%08x\n"},
292 {nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl2,
293 " APB_MISC_GP_XM2CFGD_PAD_CTRL2...: 0x%08x\n"},
294 {nvbct_lib_id_sdram_apb_misc_gp_xm2clkcfg_Pad_ctrl,
295 " APB_MISC_GP_XM2CLKCFG_PAD_CTRL..: 0x%08x\n"},
296 {nvbct_lib_id_sdram_apb_misc_gp_xm2comp_pad_ctrl,
297 " APB_MISC_GP_XM2COMP_PAD_CTRL....: 0x%08x\n"},
298 {nvbct_lib_id_sdram_apb_misc_gp_xm2vttgen_pad_ctrl,
299 " APB_MISC_GP_XM2VTTGEN_PAD_CTRL..: 0x%08x\n"},
300 };
301
302 static const char *sdram_types[nvboot_memory_type_num] = {
303 "None", "DDR", "LPDDR", "DDR2", "LPDDR2"
304 };
305
99 static void 306 static void
100 usage(void) 307 usage(void)
101 { 308 {
102 printf("Usage: bct_dump bctfile\n"); 309 printf("Usage: bct_dump bctfile\n");
103 printf(" bctfile BCT filename to read and display\n"); 310 printf(" bctfile BCT filename to read and display\n");
104 } 311 }
105 312
106 int 313 int
107 main(int argc, char *argv[]) 314 main(int argc, char *argv[])
108 { 315 {
109 int e; 316 int e;
110 build_image_context context; 317 build_image_context context;
111 u_int32_t bootloaders_used; 318 u_int32_t bootloaders_used;
112 u_int32_t parameters_used; 319 u_int32_t parameters_used;
320 u_int32_t sdram_used;
113 nvboot_dev_type type; 321 nvboot_dev_type type;
114 u_int32_t data; 322 u_int32_t data;
115 int i; 323 int i;
116 int j; 324 int j;
117 value_data const * device_values; 325 value_data const * device_values;
118 int device_count; 326 int device_count;
119 327
120 if (argc != 2) 328 if (argc != 2)
121 usage(); 329 usage();
122 330
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199 value_data value = device_values[j]; 407 value_data value = device_values[j];
200 408
201 e = context.bctlib.getdev_param(i, 409 e = context.bctlib.getdev_param(i,
202 value.id, 410 value.id,
203 &data, 411 &data,
204 context.bct); 412 context.bct);
205 printf(value.message, e == 0 ? data : -1); 413 printf(value.message, e == 0 ? data : -1);
206 } 414 }
207 } 415 }
208 416
417 /* Display SDRAM parameters sets */
418 e = context.bctlib.get_value(nvbct_lib_id_num_sdram_sets,
419 &sdram_used,
420 context.bct);
421
422 for (i = 0; (e == 0) && (i < sdram_used); ++i) {
423 printf("SDRAMParameter[%d]\n", i);
424
425 e = context.bctlib.get_sdram_params(i,
426 nvbct_lib_id_sdram_memory_type,
427 &type,
428 context.bct);
429
430 printf(" Type............................: %s\n",
431 type < nvboot_memory_type_num ? sdram_types[type]
432 : "Unknown");
433
434 for (j = 0; j < sizeof(sdram_values) / sizeof(sdram_values[0]);
435 ++j) {
436 e = context.bctlib.get_sdram_params(i,
437 sdram_values[j].id,
438 &data,
439 context.bct);
440 printf(sdram_values[j].message, e == 0 ? data : -1);
441 }
442 }
443
209 /* Clean up memory. */ 444 /* Clean up memory. */
210 cleanup_context(&context); 445 cleanup_context(&context);
211 446
212 return e; 447 return e;
213 } 448 }
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