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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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2455 void Simulator::DecodeType7(Instruction* instr) { | 2455 void Simulator::DecodeType7(Instruction* instr) { |
2456 if (instr->Bit(24) == 1) { | 2456 if (instr->Bit(24) == 1) { |
2457 SoftwareInterrupt(instr); | 2457 SoftwareInterrupt(instr); |
2458 } else { | 2458 } else { |
2459 DecodeTypeVFP(instr); | 2459 DecodeTypeVFP(instr); |
2460 } | 2460 } |
2461 } | 2461 } |
2462 | 2462 |
2463 | 2463 |
2464 // void Simulator::DecodeTypeVFP(Instruction* instr) | 2464 // void Simulator::DecodeTypeVFP(Instruction* instr) |
2465 // The Following ARMv7 VFPv instructions are currently supported. | 2465 // The Following ARMv7 VFPv instructions are currently supported. |
Karl Klose
2011/03/09 10:37:51
Please add the vneg instruction here.
Alexandre
2011/03/15 08:45:39
Done. Also added the missing vabs.
| |
2466 // vmov :Sn = Rt | 2466 // vmov :Sn = Rt |
2467 // vmov :Rt = Sn | 2467 // vmov :Rt = Sn |
2468 // vcvt: Dd = Sm | 2468 // vcvt: Dd = Sm |
2469 // vcvt: Sd = Dm | 2469 // vcvt: Sd = Dm |
2470 // Dd = vadd(Dn, Dm) | 2470 // Dd = vadd(Dn, Dm) |
2471 // Dd = vsub(Dn, Dm) | 2471 // Dd = vsub(Dn, Dm) |
2472 // Dd = vmul(Dn, Dm) | 2472 // Dd = vmul(Dn, Dm) |
2473 // Dd = vdiv(Dn, Dm) | 2473 // Dd = vdiv(Dn, Dm) |
2474 // vcmp(Dd, Dm) | 2474 // vcmp(Dd, Dm) |
2475 // vmrs | 2475 // vmrs |
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2495 } else { | 2495 } else { |
2496 int m = instr->VFPMRegValue(kSinglePrecision); | 2496 int m = instr->VFPMRegValue(kSinglePrecision); |
2497 int d = instr->VFPDRegValue(kSinglePrecision); | 2497 int d = instr->VFPDRegValue(kSinglePrecision); |
2498 set_s_register_from_float(d, get_float_from_s_register(m)); | 2498 set_s_register_from_float(d, get_float_from_s_register(m)); |
2499 } | 2499 } |
2500 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) { | 2500 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) { |
2501 // vabs | 2501 // vabs |
2502 double dm_value = get_double_from_d_register(vm); | 2502 double dm_value = get_double_from_d_register(vm); |
2503 double dd_value = fabs(dm_value); | 2503 double dd_value = fabs(dm_value); |
2504 set_d_register_from_double(vd, dd_value); | 2504 set_d_register_from_double(vd, dd_value); |
2505 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) { | |
2506 // vneg | |
2507 double dm_value = get_double_from_d_register(vm); | |
2508 double dd_value = - dm_value; | |
Karl Klose
2011/03/09 10:37:51
- dm_value -> -dm_value (no space).
Alexandre
2011/03/15 08:45:39
Done.
| |
2509 set_d_register_from_double(vd, dd_value); | |
2505 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { | 2510 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { |
2506 DecodeVCVTBetweenDoubleAndSingle(instr); | 2511 DecodeVCVTBetweenDoubleAndSingle(instr); |
2507 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { | 2512 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { |
2508 DecodeVCVTBetweenFloatingPointAndInteger(instr); | 2513 DecodeVCVTBetweenFloatingPointAndInteger(instr); |
2509 } else if (((instr->Opc2Value() >> 1) == 0x6) && | 2514 } else if (((instr->Opc2Value() >> 1) == 0x6) && |
2510 (instr->Opc3Value() & 0x1)) { | 2515 (instr->Opc3Value() & 0x1)) { |
2511 DecodeVCVTBetweenFloatingPointAndInteger(instr); | 2516 DecodeVCVTBetweenFloatingPointAndInteger(instr); |
2512 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && | 2517 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && |
2513 (instr->Opc3Value() & 0x1)) { | 2518 (instr->Opc3Value() & 0x1)) { |
2514 DecodeVCMP(instr); | 2519 DecodeVCMP(instr); |
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3156 uintptr_t address = *stack_slot; | 3161 uintptr_t address = *stack_slot; |
3157 set_register(sp, current_sp + sizeof(uintptr_t)); | 3162 set_register(sp, current_sp + sizeof(uintptr_t)); |
3158 return address; | 3163 return address; |
3159 } | 3164 } |
3160 | 3165 |
3161 } } // namespace v8::internal | 3166 } } // namespace v8::internal |
3162 | 3167 |
3163 #endif // USE_SIMULATOR | 3168 #endif // USE_SIMULATOR |
3164 | 3169 |
3165 #endif // V8_TARGET_ARCH_ARM | 3170 #endif // V8_TARGET_ARCH_ARM |
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