OLD | NEW |
1 /** | 1 /** |
2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. | 2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. |
3 * | 3 * |
4 * See file CREDITS for list of people who contributed to this | 4 * See file CREDITS for list of people who contributed to this |
5 * project. | 5 * project. |
6 * | 6 * |
7 * This program is free software; you can redistribute it and/or | 7 * This program is free software; you can redistribute it and/or |
8 * modify it under the terms of the GNU General Public License as | 8 * modify it under the terms of the GNU General Public License as |
9 * published by the Free Software Foundation; either version 2 of | 9 * published by the Free Software Foundation; either version 2 of |
10 * the License, or (at your option) any later version. | 10 * the License, or (at your option) any later version. |
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21 */ | 21 */ |
22 | 22 |
23 #include "nvbctlib.h" | 23 #include "nvbctlib.h" |
24 #include "nvboot_bct.h" | 24 #include "nvboot_bct.h" |
25 #include "string.h" | 25 #include "string.h" |
26 #include "cbootimage.h" | 26 #include "cbootimage.h" |
27 | 27 |
28 /* nvbctlib_ap20.c: The implementation of the nvbctlib API for AP20. */ | 28 /* nvbctlib_ap20.c: The implementation of the nvbctlib API for AP20. */ |
29 | 29 |
30 /* Definitions that simplify the code which follows. */ | 30 /* Definitions that simplify the code which follows. */ |
| 31 #define CASE_GET_SDRAM_PARAM(x) \ |
| 32 case nvbct_lib_id_sdram_##x:\ |
| 33 *data = bct_ptr->sdram_params[set].x; \ |
| 34 break |
| 35 |
| 36 #define CASE_SET_SDRAM_PARAM(x) \ |
| 37 case nvbct_lib_id_sdram_##x:\ |
| 38 bct_ptr->sdram_params[set].x = data; \ |
| 39 break |
| 40 |
31 #define CASE_GET_DEV_PARAM(dev, x) \ | 41 #define CASE_GET_DEV_PARAM(dev, x) \ |
32 case nvbct_lib_id_##dev##_##x:\ | 42 case nvbct_lib_id_##dev##_##x:\ |
33 *data = bct_ptr->dev_params[set].dev##_params.x; \ | 43 *data = bct_ptr->dev_params[set].dev##_params.x; \ |
34 break | 44 break |
35 | 45 |
36 #define CASE_SET_DEV_PARAM(dev, x) \ | 46 #define CASE_SET_DEV_PARAM(dev, x) \ |
37 case nvbct_lib_id_##dev##_##x:\ | 47 case nvbct_lib_id_##dev##_##x:\ |
38 bct_ptr->dev_params[set].dev##_params.x = data; \ | 48 bct_ptr->dev_params[set].dev##_params.x = data; \ |
39 break | 49 break |
40 | 50 |
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76 *length = size;\ | 86 *length = size;\ |
77 break | 87 break |
78 | 88 |
79 #define CASE_SET_DATA(id, size) \ | 89 #define CASE_SET_DATA(id, size) \ |
80 case nvbct_lib_id_##id:\ | 90 case nvbct_lib_id_##id:\ |
81 if (length < size) return -ENODATA;\ | 91 if (length < size) return -ENODATA;\ |
82 memcpy(&(bct_ptr->id), data, size); \ | 92 memcpy(&(bct_ptr->id), data, size); \ |
83 break | 93 break |
84 | 94 |
85 static int | 95 static int |
| 96 get_sdram_params(u_int32_t set, |
| 97 nvbct_lib_id id, |
| 98 u_int32_t *data, |
| 99 u_int8_t *bct) |
| 100 { |
| 101 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; |
| 102 |
| 103 if (set >= NVBOOT_BCT_MAX_SDRAM_SETS) |
| 104 return ENODATA; |
| 105 if (data == NULL || bct == NULL) |
| 106 return -ENODATA; |
| 107 |
| 108 switch (id) { |
| 109 |
| 110 CASE_GET_SDRAM_PARAM(memory_type); |
| 111 CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); |
| 112 CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); |
| 113 CASE_GET_SDRAM_PARAM(pllm_input_divider); |
| 114 CASE_GET_SDRAM_PARAM(pllm_feedback_divider); |
| 115 CASE_GET_SDRAM_PARAM(pllm_post_divider); |
| 116 CASE_GET_SDRAM_PARAM(pllm_stable_time); |
| 117 CASE_GET_SDRAM_PARAM(emc_clock_divider); |
| 118 CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); |
| 119 CASE_GET_SDRAM_PARAM(emc_auto_cal_config); |
| 120 CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); |
| 121 CASE_GET_SDRAM_PARAM(emc_pin_program_wait); |
| 122 CASE_GET_SDRAM_PARAM(emc_rc); |
| 123 CASE_GET_SDRAM_PARAM(emc_rfc); |
| 124 CASE_GET_SDRAM_PARAM(emc_ras); |
| 125 CASE_GET_SDRAM_PARAM(emc_rp); |
| 126 CASE_GET_SDRAM_PARAM(emc_r2w); |
| 127 CASE_GET_SDRAM_PARAM(emc_w2r); |
| 128 CASE_GET_SDRAM_PARAM(emc_r2p); |
| 129 CASE_GET_SDRAM_PARAM(emc_w2p); |
| 130 CASE_GET_SDRAM_PARAM(emc_rd_rcd); |
| 131 CASE_GET_SDRAM_PARAM(emc_wr_rcd); |
| 132 CASE_GET_SDRAM_PARAM(emc_rrd); |
| 133 CASE_GET_SDRAM_PARAM(emc_rext); |
| 134 CASE_GET_SDRAM_PARAM(emc_wdv); |
| 135 CASE_GET_SDRAM_PARAM(emc_quse); |
| 136 CASE_GET_SDRAM_PARAM(emc_qrst); |
| 137 CASE_GET_SDRAM_PARAM(emc_qsafe); |
| 138 CASE_GET_SDRAM_PARAM(emc_rdv); |
| 139 CASE_GET_SDRAM_PARAM(emc_refresh); |
| 140 CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); |
| 141 CASE_GET_SDRAM_PARAM(emc_pdex2wr); |
| 142 CASE_GET_SDRAM_PARAM(emc_pdex2rd); |
| 143 CASE_GET_SDRAM_PARAM(emc_pchg2pden); |
| 144 CASE_GET_SDRAM_PARAM(emc_act2pden); |
| 145 CASE_GET_SDRAM_PARAM(emc_ar2pden); |
| 146 CASE_GET_SDRAM_PARAM(emc_rw2pden); |
| 147 CASE_GET_SDRAM_PARAM(emc_txsr); |
| 148 CASE_GET_SDRAM_PARAM(emc_tcke); |
| 149 CASE_GET_SDRAM_PARAM(emc_tfaw); |
| 150 CASE_GET_SDRAM_PARAM(emc_trpab); |
| 151 CASE_GET_SDRAM_PARAM(emc_tclkstable); |
| 152 CASE_GET_SDRAM_PARAM(emc_tclkstop); |
| 153 CASE_GET_SDRAM_PARAM(emc_trefbw); |
| 154 CASE_GET_SDRAM_PARAM(emc_quse_extra); |
| 155 CASE_GET_SDRAM_PARAM(emc_fbio_cfg1); |
| 156 CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly); |
| 157 CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); |
| 158 CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly); |
| 159 CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb); |
| 160 CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); |
| 161 CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); |
| 162 CASE_GET_SDRAM_PARAM(emc_fbio_spare); |
| 163 CASE_GET_SDRAM_PARAM(emc_mrs); |
| 164 CASE_GET_SDRAM_PARAM(emc_emrs); |
| 165 CASE_GET_SDRAM_PARAM(emc_mrw1); |
| 166 CASE_GET_SDRAM_PARAM(emc_mrw2); |
| 167 CASE_GET_SDRAM_PARAM(emc_mrw3); |
| 168 CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); |
| 169 CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); |
| 170 CASE_GET_SDRAM_PARAM(emc_adr_cfg); |
| 171 CASE_GET_SDRAM_PARAM(emc_adr_cfg1); |
| 172 CASE_GET_SDRAM_PARAM(mc_emem_Cfg); |
| 173 CASE_GET_SDRAM_PARAM(mc_lowlatency_config); |
| 174 CASE_GET_SDRAM_PARAM(emc_cfg); |
| 175 CASE_GET_SDRAM_PARAM(emc_cfg2); |
| 176 CASE_GET_SDRAM_PARAM(emc_dbg); |
| 177 CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); |
| 178 CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); |
| 179 CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs); |
| 180 CASE_GET_SDRAM_PARAM(emc_dll_xform_quse); |
| 181 CASE_GET_SDRAM_PARAM(warm_boot_wait); |
| 182 CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); |
| 183 CASE_GET_SDRAM_PARAM(emc_odt_write); |
| 184 CASE_GET_SDRAM_PARAM(emc_odt_read); |
| 185 CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt); |
| 186 CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); |
| 187 CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); |
| 188 CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); |
| 189 CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0); |
| 190 CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1); |
| 191 CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait); |
| 192 CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); |
| 193 CASE_GET_SDRAM_PARAM(emc_emrs_emr2); |
| 194 CASE_GET_SDRAM_PARAM(emc_emrs_emr3); |
| 195 CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); |
| 196 CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); |
| 197 CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); |
| 198 CASE_GET_SDRAM_PARAM(emc_ddr2_wait); |
| 199 CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0); |
| 200 CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1); |
| 201 CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2); |
| 202 CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); |
| 203 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); |
| 204 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); |
| 205 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); |
| 206 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); |
| 207 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); |
| 208 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); |
| 209 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); |
| 210 CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); |
| 211 |
| 212 default: |
| 213 return -ENODATA; |
| 214 } |
| 215 |
| 216 return 0; |
| 217 |
| 218 } |
| 219 |
| 220 static int |
| 221 set_sdram_params(u_int32_t set, |
| 222 nvbct_lib_id id, |
| 223 u_int32_t data, |
| 224 u_int8_t *bct) |
| 225 { |
| 226 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; |
| 227 |
| 228 if (set >= NVBOOT_BCT_MAX_SDRAM_SETS) |
| 229 return ENODATA; |
| 230 if (bct == NULL) |
| 231 return -ENODATA; |
| 232 |
| 233 switch (id) { |
| 234 |
| 235 CASE_SET_SDRAM_PARAM(memory_type); |
| 236 CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); |
| 237 CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); |
| 238 CASE_SET_SDRAM_PARAM(pllm_input_divider); |
| 239 CASE_SET_SDRAM_PARAM(pllm_feedback_divider); |
| 240 CASE_SET_SDRAM_PARAM(pllm_post_divider); |
| 241 CASE_SET_SDRAM_PARAM(pllm_stable_time); |
| 242 CASE_SET_SDRAM_PARAM(emc_clock_divider); |
| 243 CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); |
| 244 CASE_SET_SDRAM_PARAM(emc_auto_cal_config); |
| 245 CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); |
| 246 CASE_SET_SDRAM_PARAM(emc_pin_program_wait); |
| 247 CASE_SET_SDRAM_PARAM(emc_rc); |
| 248 CASE_SET_SDRAM_PARAM(emc_rfc); |
| 249 CASE_SET_SDRAM_PARAM(emc_ras); |
| 250 CASE_SET_SDRAM_PARAM(emc_rp); |
| 251 CASE_SET_SDRAM_PARAM(emc_r2w); |
| 252 CASE_SET_SDRAM_PARAM(emc_w2r); |
| 253 CASE_SET_SDRAM_PARAM(emc_r2p); |
| 254 CASE_SET_SDRAM_PARAM(emc_w2p); |
| 255 CASE_SET_SDRAM_PARAM(emc_rd_rcd); |
| 256 CASE_SET_SDRAM_PARAM(emc_wr_rcd); |
| 257 CASE_SET_SDRAM_PARAM(emc_rrd); |
| 258 CASE_SET_SDRAM_PARAM(emc_rext); |
| 259 CASE_SET_SDRAM_PARAM(emc_wdv); |
| 260 CASE_SET_SDRAM_PARAM(emc_quse); |
| 261 CASE_SET_SDRAM_PARAM(emc_qrst); |
| 262 CASE_SET_SDRAM_PARAM(emc_qsafe); |
| 263 CASE_SET_SDRAM_PARAM(emc_rdv); |
| 264 CASE_SET_SDRAM_PARAM(emc_refresh); |
| 265 CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); |
| 266 CASE_SET_SDRAM_PARAM(emc_pdex2wr); |
| 267 CASE_SET_SDRAM_PARAM(emc_pdex2rd); |
| 268 CASE_SET_SDRAM_PARAM(emc_pchg2pden); |
| 269 CASE_SET_SDRAM_PARAM(emc_act2pden); |
| 270 CASE_SET_SDRAM_PARAM(emc_ar2pden); |
| 271 CASE_SET_SDRAM_PARAM(emc_rw2pden); |
| 272 CASE_SET_SDRAM_PARAM(emc_txsr); |
| 273 CASE_SET_SDRAM_PARAM(emc_tcke); |
| 274 CASE_SET_SDRAM_PARAM(emc_tfaw); |
| 275 CASE_SET_SDRAM_PARAM(emc_trpab); |
| 276 CASE_SET_SDRAM_PARAM(emc_tclkstable); |
| 277 CASE_SET_SDRAM_PARAM(emc_tclkstop); |
| 278 CASE_SET_SDRAM_PARAM(emc_trefbw); |
| 279 CASE_SET_SDRAM_PARAM(emc_quse_extra); |
| 280 CASE_SET_SDRAM_PARAM(emc_fbio_cfg1); |
| 281 CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly); |
| 282 CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); |
| 283 CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly); |
| 284 CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly_msb); |
| 285 CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); |
| 286 CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); |
| 287 CASE_SET_SDRAM_PARAM(emc_fbio_spare); |
| 288 CASE_SET_SDRAM_PARAM(emc_mrs); |
| 289 CASE_SET_SDRAM_PARAM(emc_emrs); |
| 290 CASE_SET_SDRAM_PARAM(emc_mrw1); |
| 291 CASE_SET_SDRAM_PARAM(emc_mrw2); |
| 292 CASE_SET_SDRAM_PARAM(emc_mrw3); |
| 293 CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); |
| 294 CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); |
| 295 CASE_SET_SDRAM_PARAM(emc_adr_cfg); |
| 296 CASE_SET_SDRAM_PARAM(emc_adr_cfg1); |
| 297 CASE_SET_SDRAM_PARAM(mc_emem_Cfg); |
| 298 CASE_SET_SDRAM_PARAM(mc_lowlatency_config); |
| 299 CASE_SET_SDRAM_PARAM(emc_cfg); |
| 300 CASE_SET_SDRAM_PARAM(emc_cfg2); |
| 301 CASE_SET_SDRAM_PARAM(emc_dbg); |
| 302 CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); |
| 303 CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); |
| 304 CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs); |
| 305 CASE_SET_SDRAM_PARAM(emc_dll_xform_quse); |
| 306 CASE_SET_SDRAM_PARAM(warm_boot_wait); |
| 307 CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); |
| 308 CASE_SET_SDRAM_PARAM(emc_odt_write); |
| 309 CASE_SET_SDRAM_PARAM(emc_odt_read); |
| 310 CASE_SET_SDRAM_PARAM(emc_zcal_ref_cnt); |
| 311 CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); |
| 312 CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); |
| 313 CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); |
| 314 CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev0); |
| 315 CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev1); |
| 316 CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_wait); |
| 317 CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); |
| 318 CASE_SET_SDRAM_PARAM(emc_emrs_emr2); |
| 319 CASE_SET_SDRAM_PARAM(emc_emrs_emr3); |
| 320 CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); |
| 321 CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); |
| 322 CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); |
| 323 CASE_SET_SDRAM_PARAM(emc_ddr2_wait); |
| 324 CASE_SET_SDRAM_PARAM(emc_cfg_clktrim0); |
| 325 CASE_SET_SDRAM_PARAM(emc_cfg_clktrim1); |
| 326 CASE_SET_SDRAM_PARAM(emc_cfg_clktrim2); |
| 327 CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); |
| 328 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); |
| 329 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); |
| 330 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); |
| 331 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); |
| 332 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); |
| 333 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); |
| 334 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); |
| 335 CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); |
| 336 |
| 337 default: |
| 338 return -ENODATA; |
| 339 } |
| 340 |
| 341 return 0; |
| 342 } |
| 343 static int |
86 getdev_param(u_int32_t set, | 344 getdev_param(u_int32_t set, |
87 nvbct_lib_id id, | 345 nvbct_lib_id id, |
88 u_int32_t *data, | 346 u_int32_t *data, |
89 u_int8_t *bct) | 347 u_int8_t *bct) |
90 { | 348 { |
91 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; | 349 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; |
92 | 350 |
93 if (data == NULL || bct == NULL) | 351 if (data == NULL || bct == NULL) |
94 return -ENODATA; | 352 return -ENODATA; |
95 | 353 |
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244 | 502 |
245 switch (id) { | 503 switch (id) { |
246 /* | 504 /* |
247 * Simple BCT fields | 505 * Simple BCT fields |
248 */ | 506 */ |
249 CASE_GET_NVU32(boot_data_version); | 507 CASE_GET_NVU32(boot_data_version); |
250 CASE_GET_NVU32(block_size_log2); | 508 CASE_GET_NVU32(block_size_log2); |
251 CASE_GET_NVU32(page_size_log2); | 509 CASE_GET_NVU32(page_size_log2); |
252 CASE_GET_NVU32(partition_size); | 510 CASE_GET_NVU32(partition_size); |
253 CASE_GET_NVU32(num_param_sets); | 511 CASE_GET_NVU32(num_param_sets); |
| 512 CASE_GET_NVU32(num_sdram_sets); |
254 CASE_GET_NVU32(bootloader_used); | 513 CASE_GET_NVU32(bootloader_used); |
255 | 514 |
256 /* | 515 /* |
257 * Constants. | 516 * Constants. |
258 */ | 517 */ |
259 | 518 |
260 CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); | 519 CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); |
261 CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); | 520 CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); |
262 | 521 |
263 case nvbct_lib_id_reserved_offset: | 522 case nvbct_lib_id_reserved_offset: |
(...skipping 23 matching lines...) Expand all Loading... |
287 CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); | 546 CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); |
288 CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); | 547 CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); |
289 CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); | 548 CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); |
290 CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); | 549 CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); |
291 CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); | 550 CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); |
292 CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); | 551 CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); |
293 CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); | 552 CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); |
294 CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); | 553 CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); |
295 CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); | 554 CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); |
296 | 555 |
| 556 CASE_GET_CONST_PREFIX(memory_type_none, nvboot); |
| 557 CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); |
| 558 CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); |
| 559 CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); |
| 560 CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); |
| 561 |
297 default: | 562 default: |
298 return -ENODATA; | 563 return -ENODATA; |
299 } | 564 } |
300 return 0; | 565 return 0; |
301 } | 566 } |
302 | 567 |
303 static int | 568 static int |
304 bct_set_value(nvbct_lib_id id, u_int32_t data, u_int8_t *bct) | 569 bct_set_value(nvbct_lib_id id, u_int32_t data, u_int8_t *bct) |
305 { | 570 { |
306 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; | 571 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; |
307 | 572 |
308 if (bct == NULL) | 573 if (bct == NULL) |
309 return -ENODATA; | 574 return -ENODATA; |
310 | 575 |
311 switch (id) { | 576 switch (id) { |
312 /* | 577 /* |
313 * Simple BCT fields | 578 * Simple BCT fields |
314 */ | 579 */ |
315 CASE_SET_NVU32(boot_data_version); | 580 CASE_SET_NVU32(boot_data_version); |
316 CASE_SET_NVU32(block_size_log2); | 581 CASE_SET_NVU32(block_size_log2); |
317 CASE_SET_NVU32(page_size_log2); | 582 CASE_SET_NVU32(page_size_log2); |
318 CASE_SET_NVU32(partition_size); | 583 CASE_SET_NVU32(partition_size); |
319 CASE_SET_NVU32(num_param_sets); | 584 CASE_SET_NVU32(num_param_sets); |
| 585 CASE_SET_NVU32(num_sdram_sets); |
320 CASE_SET_NVU32(bootloader_used); | 586 CASE_SET_NVU32(bootloader_used); |
321 | 587 |
322 default: | 588 default: |
323 return -ENODATA; | 589 return -ENODATA; |
324 } | 590 } |
325 | 591 |
326 return 0; | 592 return 0; |
327 } | 593 } |
328 | 594 |
329 | 595 |
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372 | 638 |
373 fns->get_data = bct_get_data; | 639 fns->get_data = bct_get_data; |
374 fns->set_data = bct_set_data; | 640 fns->set_data = bct_set_data; |
375 | 641 |
376 fns->getbl_param = getbl_param; | 642 fns->getbl_param = getbl_param; |
377 fns->setbl_param = setbl_param; | 643 fns->setbl_param = setbl_param; |
378 | 644 |
379 fns->getdev_param = getdev_param; | 645 fns->getdev_param = getdev_param; |
380 fns->setdev_param = setdev_param; | 646 fns->setdev_param = setdev_param; |
381 | 647 |
| 648 fns->get_sdram_params = get_sdram_params; |
| 649 fns->set_sdram_params = set_sdram_params; |
382 } | 650 } |
OLD | NEW |