Chromium: arm: tegra: Add NAND support

include/configs/chromeos/tegra2/seaboard/parts/nand.h

Index: include/configs/chromeos/tegra2/seaboard/parts/nand.h
diff --git a/include/configs/chromeos/tegra2/seaboard/parts/nand.h b/include/configs/chromeos/tegra2/seaboard/parts/nand.h
new file mode 100644
index 0000000000000000000000000000000000000000..084588a61bc0c9027b1e7f115a17c97d67b6c937
--- /dev/null
+++ b/include/configs/chromeos/tegra2/seaboard/parts/nand.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+/* Set clock divisor
+ * 7 bits of D and 1 bit of H
+ * divisor= (DDDDDDD + 1) + (H x 0.5)
+ * clock = original clock / divisor
+ * 6 means /4  */
+#define CONFIG_NAND_CLK_DIVISOR_DDDDDDDH	6
+
+#ifdef CONFIG_TEGRA2_NAND_HYNIX_HY27UF4G2B
+/* For HYNIX HY27UF4G2B
+ * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz
+ * to CLK_RST_CONTROLLER_PLLP_BASE_0,
+ * 216MHz / divisor 4 = 54MHZ
+ * 1 clock = 18.5 ns = NAND_CLK_PERIOD
+ * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode
+ *   bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5
+ * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24)
+ * similar way for other fields, please refer to reference manual
+ */
+/* Value to be set to NAND_TIMING_0 register, address=70008014h */
+#define CONFIG_TEGRA2_NAND_TIMING	0x15040001
+/* Value to be set to NAND_TIMING2_0 register, address=7000801Ch */
+#define CONFIG_TEGRA2_NAND_TIMING2	0x01
+#endif