Chromium: arm: tegra: Add NAND support

include/configs/tegra2_harmony.h

Index: include/configs/tegra2_harmony.h
diff --git a/include/configs/tegra2_harmony.h b/include/configs/tegra2_harmony.h
index bfe8794319b9036beb4e8d5c54c5fee592dfcb33..5bdb1e01a743c4da9ee77ca0f4f0bdb8ba88b499 100644
--- a/include/configs/tegra2_harmony.h
+++ b/include/configs/tegra2_harmony.h
@@ -74,4 +74,21 @@
 #define CONFIG_LCD_vl_row	600
 #endif
 
+/* For HYNIX HY27UF4G2B
+ * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz
+ * to CLK_RST_CONTROLLER_PLLP_BASE_0,
+ * 216MHz / divisor 4 = 54MHZ
+ * 1 clock = 18.5 ns = NAND_CLK_PERIOD
+ * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode
+ *   bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5
+ * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24)
+ * similar way for other fields, please refer to reference manual
+ */
+/* Value to be set to NAND_TIMING_0 register, address=70008014h */
+#define CONFIG_TEGRA2_NAND_TIMING	0x15040001
+/* Value to be set to NAND_TIMING2_0 register, address=7000801Ch  */
+#define CONFIG_TEGRA2_NAND_TIMING2	0x01
+/* tR = Time taken for data transfer from NAND cell to NAND register,
+ * in micro-second */
+#define CONFIG_TEGRA2_NAND_tR_US	25
 #endif /* __CONFIG_H */