include/configs/tegra2_harmony.h - Issue 6623073: Chromium: arm: tegra: Add NAND support

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Side by Side Diff: include/configs/tegra2_harmony.h

Issue 6623073: Chromium: arm: tegra: Add NAND support (Closed) Base URL: http://git.chromium.org/git/u-boot-next.git@chromeos-v2010.09

Patch Set: Remove folder HY27UF084G2B, move timing value to config file. Created 9 years, 9 months ago

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1 /*	1 /*

2 * (C) Copyright 2010	2 * (C) Copyright 2010

3 * NVIDIA Corporation <www.nvidia.com>	3 * NVIDIA Corporation <www.nvidia.com>

4 *	4 *

5 * See file CREDITS for list of people who contributed to this	5 * See file CREDITS for list of people who contributed to this

6 * project.	6 * project.

7 *	7 *

8 * This program is free software; you can redistribute it and/or	8 * This program is free software; you can redistribute it and/or

9 * modify it under the terms of the GNU General Public License as	9 * modify it under the terms of the GNU General Public License as

10 * published by the Free Software Foundation; either version 2 of	10 * published by the Free Software Foundation; either version 2 of

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67 #define NvUSBx_1 USB_EHCI_TEGRA_BASE_ADDR_USB1	67 #define NvUSBx_1 USB_EHCI_TEGRA_BASE_ADDR_USB1

68 #define NvUSBx_2 0	68 #define NvUSBx_2 0

69 #define NvUSBx_3 0	69 #define NvUSBx_3 0

70	70

71 /* LCD Settings */	71 /* LCD Settings */

72 #ifdef CONFIG_LCD	72 #ifdef CONFIG_LCD

73 #define CONFIG_LCD_vl_col 1024	73 #define CONFIG_LCD_vl_col 1024

74 #define CONFIG_LCD_vl_row 600	74 #define CONFIG_LCD_vl_row 600

75 #endif	75 #endif

76	76

	77 /* For HYNIX HY27UF4G2B

	78 * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz

	79 * to CLK_RST_CONTROLLER_PLLP_BASE_0,

	80 * 216MHz / divisor 4 = 54MHZ

	81 * 1 clock = 18.5 ns = NAND_CLK_PERIOD

	82 * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode

	83 * bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5

	84 * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24)

	85 * similar way for other fields, please refer to reference manual

	86 */

	87 /* Value to be set to NAND_TIMING_0 register, address=70008014h */

	88 #define CONFIG_TEGRA2_NAND_TIMING 0x15040001

	89 /* Value to be set to NAND_TIMING2_0 register, address=7000801Ch */

	90 #define CONFIG_TEGRA2_NAND_TIMING2 0x01

	91 /* tR = Time taken for data transfer from NAND cell to NAND register,

	92 * in micro-second */

	93 #define CONFIG_TEGRA2_NAND_tR_US 25

77 #endif /* __CONFIG_H */	94 #endif /* __CONFIG_H */

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