| OLD | NEW |
| (Empty) | |
| 1 /* register offset */ |
| 2 #define NAND_COMMAND_0 0x00 |
| 3 #define NAND_STATUS_0 0x04 |
| 4 #define NAND_ISR_0 0x08 |
| 5 #define NAND_IER_0 0x0C |
| 6 #define NAND_CONFIG_0 0x10 |
| 7 #define NAND_TIMING_0 0x14 |
| 8 #define NAND_RESP_0 0x18 |
| 9 #define NAND_TIMING2_0 0x1C |
| 10 #define NAND_CMD_REG1_0 0x20 |
| 11 #define NAND_CMD_REG2_0 0x24 |
| 12 #define NAND_ADDR_REG1_0 0x28 |
| 13 #define NAND_ADDR_REG2_0 0x2C |
| 14 |
| 15 #define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR) |
| 16 |
| 17 static uint8_t tegra2_nand_read_byte(struct mtd_info *mtd); |
| 18 static void tegra2_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int
len); |
| 19 static void tegra2_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); |
| 20 static int tegra2_nand_waitfor_GO_cleared(struct mtd_info *mtd); |
| 21 static int tegra2_nand_dev_ready(struct mtd_info *mtd); |
| 22 |
| 23 |
| 24 |
| OLD | NEW |