Chromium: arm: tegra: Add NAND support

board/tegra2/common/board.c

 /*
  *  (C) Copyright 2010
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ skipping 154 matching lines @@
  *              hardware. Many pins need to be moved from protect to primary
  *              mode.
  */
 void set_muxconf_regs(void)
 {
 }
 
 /***************************************************************************
  * Routines to be provided by corresponding device drivers.
  ***************************************************************************/
+#ifndef CONFIG_NAND_TEGRA2

[Tom Warren, 2011/03/08 20:43:08]

This should be CONFIG_TEGRA2_NAND, just like _SPI, _I2C, etc.

 int board_nand_init(struct nand_chip *nand)
 {
     return -1;
 }
+#endif
 
 /***************************************************************************
  * Routines for UART initialization.
  ***************************************************************************/
 void
 NvBlAvpClockSetDivider(NvBool Enable, NvU32 Dividened, NvU32 Divisor)
 {
     NvU32 val;
 
     if (Enable)
@@ skipping 537 matching lines @@
         RegVal= readl(NV_ADDRESS_MAP_USB3_BASE+UTMIP_XCVR_CFG1);
         RegVal &= ~(Bit4+Bit2+Bit0);
         writel(RegVal, NV_ADDRESS_MAP_USB3_BASE+UTMIP_XCVR_CFG1);
 
 #if ((LINUX_MACH_TYPE == MACH_TYPE_SEABOARD) || \
      (LINUX_MACH_TYPE == MACH_TYPE_KAEN) || \
      (LINUX_MACH_TYPE == MACH_TYPE_AEBL))
         usb1_set_host_mode();
 #endif
 }