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Side by Side Diff: nvbctlib_ap20.c

Issue 6611009: Add the nand device support for cbootimage tool. (Closed) Base URL: http://git.chromium.org/git/cbootimage.git@master
Patch Set: Created 9 years, 9 months ago
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1 /** 1 /**
2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2011 NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
(...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after
87 nvbct_lib_id id, 87 nvbct_lib_id id,
88 u_int32_t *data, 88 u_int32_t *data,
89 u_int8_t *bct) 89 u_int8_t *bct)
90 { 90 {
91 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; 91 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct;
92 92
93 if (data == NULL || bct == NULL) 93 if (data == NULL || bct == NULL)
94 return -ENODATA; 94 return -ENODATA;
95 95
96 switch (id) { 96 switch (id) {
97 CASE_GET_DEV_PARAM(nand, clock_divider);
98 CASE_GET_DEV_PARAM(nand, nand_timing);
99 CASE_GET_DEV_PARAM(nand, nand_timing2);
100 CASE_GET_DEV_PARAM(nand, block_size_log2);
101 CASE_GET_DEV_PARAM(nand, page_size_log2);
102
97 CASE_GET_DEV_PARAM(sdmmc, clock_divider); 103 CASE_GET_DEV_PARAM(sdmmc, clock_divider);
98 CASE_GET_DEV_PARAM(sdmmc, data_width); 104 CASE_GET_DEV_PARAM(sdmmc, data_width);
99 CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); 105 CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported);
100 106
101 CASE_GET_DEV_PARAM(spiflash, clock_source); 107 CASE_GET_DEV_PARAM(spiflash, clock_source);
102 CASE_GET_DEV_PARAM(spiflash, clock_divider); 108 CASE_GET_DEV_PARAM(spiflash, clock_divider);
103 CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); 109 CASE_GET_DEV_PARAM(spiflash, read_command_type_fast);
104 110
105 case nvbct_lib_id_dev_type: 111 case nvbct_lib_id_dev_type:
106 *data = bct_ptr->dev_type[set]; 112 *data = bct_ptr->dev_type[set];
(...skipping 11 matching lines...) Expand all
118 nvbct_lib_id id, 124 nvbct_lib_id id,
119 u_int32_t data, 125 u_int32_t data,
120 u_int8_t *bct) 126 u_int8_t *bct)
121 { 127 {
122 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct; 128 nvboot_config_table *bct_ptr = (nvboot_config_table*)bct;
123 129
124 if (bct == NULL) 130 if (bct == NULL)
125 return -ENODATA; 131 return -ENODATA;
126 132
127 switch (id) { 133 switch (id) {
134 CASE_SET_DEV_PARAM(nand, clock_divider);
135 CASE_SET_DEV_PARAM(nand, nand_timing);
136 CASE_SET_DEV_PARAM(nand, nand_timing2);
137 CASE_SET_DEV_PARAM(nand, block_size_log2);
138 CASE_SET_DEV_PARAM(nand, page_size_log2);
139
128 CASE_SET_DEV_PARAM(sdmmc, clock_divider); 140 CASE_SET_DEV_PARAM(sdmmc, clock_divider);
129 CASE_SET_DEV_PARAM(sdmmc, data_width); 141 CASE_SET_DEV_PARAM(sdmmc, data_width);
130 CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); 142 CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported);
131 143
132 CASE_SET_DEV_PARAM(spiflash, clock_source); 144 CASE_SET_DEV_PARAM(spiflash, clock_source);
133 CASE_SET_DEV_PARAM(spiflash, clock_divider); 145 CASE_SET_DEV_PARAM(spiflash, clock_divider);
134 CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); 146 CASE_SET_DEV_PARAM(spiflash, read_command_type_fast);
135 147
136 case nvbct_lib_id_dev_type: 148 case nvbct_lib_id_dev_type:
137 bct_ptr->dev_type[set] = data; 149 bct_ptr->dev_type[set] = data;
(...skipping 127 matching lines...) Expand 10 before | Expand all | Expand 10 after
265 - (u_int8_t*)&samplebct; 277 - (u_int8_t*)&samplebct;
266 break; 278 break;
267 279
268 case nvbct_lib_id_crypto_length: 280 case nvbct_lib_id_crypto_length:
269 /* size of region in BCT to encrypt & sign */ 281 /* size of region in BCT to encrypt & sign */
270 *data = sizeof(nvboot_config_table) - sizeof(nvboot_hash); 282 *data = sizeof(nvboot_config_table) - sizeof(nvboot_hash);
271 break; 283 break;
272 284
273 CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); 285 CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS);
274 286
287 CASE_GET_CONST_PREFIX(dev_type_nand, nvboot);
275 CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); 288 CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot);
276 CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); 289 CASE_GET_CONST_PREFIX(dev_type_spi, nvboot);
277 CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); 290 CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot);
278 CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); 291 CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot);
279 CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); 292 CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot);
280 CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); 293 CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot);
281 CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); 294 CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot);
282 CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); 295 CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot);
283 296
284 default: 297 default:
(...skipping 75 matching lines...) Expand 10 before | Expand all | Expand 10 after
360 fns->get_data = bct_get_data; 373 fns->get_data = bct_get_data;
361 fns->set_data = bct_set_data; 374 fns->set_data = bct_set_data;
362 375
363 fns->getbl_param = getbl_param; 376 fns->getbl_param = getbl_param;
364 fns->setbl_param = setbl_param; 377 fns->setbl_param = setbl_param;
365 378
366 fns->getdev_param = getdev_param; 379 fns->getdev_param = getdev_param;
367 fns->setdev_param = setdev_param; 380 fns->setdev_param = setdev_param;
368 381
369 } 382 }
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