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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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77 } | 77 } |
78 int bit() const { | 78 int bit() const { |
79 ASSERT(is_valid()); | 79 ASSERT(is_valid()); |
80 return 1 << code_; | 80 return 1 << code_; |
81 } | 81 } |
82 | 82 |
83 // Unfortunately we can't make this private in a struct. | 83 // Unfortunately we can't make this private in a struct. |
84 int code_; | 84 int code_; |
85 }; | 85 }; |
86 | 86 |
| 87 const Register no_reg = { -1 }; |
87 | 88 |
88 extern Register no_reg; | 89 const Register r0 = { 0 }; |
89 extern Register r0; | 90 const Register r1 = { 1 }; |
90 extern Register r1; | 91 const Register r2 = { 2 }; |
91 extern Register r2; | 92 const Register r3 = { 3 }; |
92 extern Register r3; | 93 const Register r4 = { 4 }; |
93 extern Register r4; | 94 const Register r5 = { 5 }; |
94 extern Register r5; | 95 const Register r6 = { 6 }; |
95 extern Register r6; | 96 const Register r7 = { 7 }; |
96 extern Register r7; | 97 const Register r8 = { 8 }; // Used as context register. |
97 extern Register r8; | 98 const Register r9 = { 9 }; |
98 extern Register r9; | 99 const Register r10 = { 10 }; // Used as roots register. |
99 extern Register r10; | 100 const Register fp = { 11 }; |
100 extern Register fp; | 101 const Register ip = { 12 }; |
101 extern Register ip; | 102 const Register sp = { 13 }; |
102 extern Register sp; | 103 const Register lr = { 14 }; |
103 extern Register lr; | 104 const Register pc = { 15 }; |
104 extern Register pc; | |
105 | |
106 | 105 |
107 // Single word VFP register. | 106 // Single word VFP register. |
108 struct SwVfpRegister { | 107 struct SwVfpRegister { |
109 bool is_valid() const { return 0 <= code_ && code_ < 32; } | 108 bool is_valid() const { return 0 <= code_ && code_ < 32; } |
110 bool is(SwVfpRegister reg) const { return code_ == reg.code_; } | 109 bool is(SwVfpRegister reg) const { return code_ == reg.code_; } |
111 int code() const { | 110 int code() const { |
112 ASSERT(is_valid()); | 111 ASSERT(is_valid()); |
113 return code_; | 112 return code_; |
114 } | 113 } |
115 int bit() const { | 114 int bit() const { |
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132 } | 131 } |
133 int bit() const { | 132 int bit() const { |
134 ASSERT(is_valid()); | 133 ASSERT(is_valid()); |
135 return 1 << code_; | 134 return 1 << code_; |
136 } | 135 } |
137 | 136 |
138 int code_; | 137 int code_; |
139 }; | 138 }; |
140 | 139 |
141 | 140 |
142 // Support for VFP registers s0 to s31 (d0 to d15). | 141 // Support for the VFP registers s0 to s31 (d0 to d15). |
143 // Note that "s(N):s(N+1)" is the same as "d(N/2)". | 142 // Note that "s(N):s(N+1)" is the same as "d(N/2)". |
144 extern SwVfpRegister s0; | 143 const SwVfpRegister s0 = { 0 }; |
145 extern SwVfpRegister s1; | 144 const SwVfpRegister s1 = { 1 }; |
146 extern SwVfpRegister s2; | 145 const SwVfpRegister s2 = { 2 }; |
147 extern SwVfpRegister s3; | 146 const SwVfpRegister s3 = { 3 }; |
148 extern SwVfpRegister s4; | 147 const SwVfpRegister s4 = { 4 }; |
149 extern SwVfpRegister s5; | 148 const SwVfpRegister s5 = { 5 }; |
150 extern SwVfpRegister s6; | 149 const SwVfpRegister s6 = { 6 }; |
151 extern SwVfpRegister s7; | 150 const SwVfpRegister s7 = { 7 }; |
152 extern SwVfpRegister s8; | 151 const SwVfpRegister s8 = { 8 }; |
153 extern SwVfpRegister s9; | 152 const SwVfpRegister s9 = { 9 }; |
154 extern SwVfpRegister s10; | 153 const SwVfpRegister s10 = { 10 }; |
155 extern SwVfpRegister s11; | 154 const SwVfpRegister s11 = { 11 }; |
156 extern SwVfpRegister s12; | 155 const SwVfpRegister s12 = { 12 }; |
157 extern SwVfpRegister s13; | 156 const SwVfpRegister s13 = { 13 }; |
158 extern SwVfpRegister s14; | 157 const SwVfpRegister s14 = { 14 }; |
159 extern SwVfpRegister s15; | 158 const SwVfpRegister s15 = { 15 }; |
160 extern SwVfpRegister s16; | 159 const SwVfpRegister s16 = { 16 }; |
161 extern SwVfpRegister s17; | 160 const SwVfpRegister s17 = { 17 }; |
162 extern SwVfpRegister s18; | 161 const SwVfpRegister s18 = { 18 }; |
163 extern SwVfpRegister s19; | 162 const SwVfpRegister s19 = { 19 }; |
164 extern SwVfpRegister s20; | 163 const SwVfpRegister s20 = { 20 }; |
165 extern SwVfpRegister s21; | 164 const SwVfpRegister s21 = { 21 }; |
166 extern SwVfpRegister s22; | 165 const SwVfpRegister s22 = { 22 }; |
167 extern SwVfpRegister s23; | 166 const SwVfpRegister s23 = { 23 }; |
168 extern SwVfpRegister s24; | 167 const SwVfpRegister s24 = { 24 }; |
169 extern SwVfpRegister s25; | 168 const SwVfpRegister s25 = { 25 }; |
170 extern SwVfpRegister s26; | 169 const SwVfpRegister s26 = { 26 }; |
171 extern SwVfpRegister s27; | 170 const SwVfpRegister s27 = { 27 }; |
172 extern SwVfpRegister s28; | 171 const SwVfpRegister s28 = { 28 }; |
173 extern SwVfpRegister s29; | 172 const SwVfpRegister s29 = { 29 }; |
174 extern SwVfpRegister s30; | 173 const SwVfpRegister s30 = { 30 }; |
175 extern SwVfpRegister s31; | 174 const SwVfpRegister s31 = { 31 }; |
176 | 175 |
177 extern DwVfpRegister d0; | 176 const DwVfpRegister d0 = { 0 }; |
178 extern DwVfpRegister d1; | 177 const DwVfpRegister d1 = { 1 }; |
179 extern DwVfpRegister d2; | 178 const DwVfpRegister d2 = { 2 }; |
180 extern DwVfpRegister d3; | 179 const DwVfpRegister d3 = { 3 }; |
181 extern DwVfpRegister d4; | 180 const DwVfpRegister d4 = { 4 }; |
182 extern DwVfpRegister d5; | 181 const DwVfpRegister d5 = { 5 }; |
183 extern DwVfpRegister d6; | 182 const DwVfpRegister d6 = { 6 }; |
184 extern DwVfpRegister d7; | 183 const DwVfpRegister d7 = { 7 }; |
185 extern DwVfpRegister d8; | 184 const DwVfpRegister d8 = { 8 }; |
186 extern DwVfpRegister d9; | 185 const DwVfpRegister d9 = { 9 }; |
187 extern DwVfpRegister d10; | 186 const DwVfpRegister d10 = { 10 }; |
188 extern DwVfpRegister d11; | 187 const DwVfpRegister d11 = { 11 }; |
189 extern DwVfpRegister d12; | 188 const DwVfpRegister d12 = { 12 }; |
190 extern DwVfpRegister d13; | 189 const DwVfpRegister d13 = { 13 }; |
191 extern DwVfpRegister d14; | 190 const DwVfpRegister d14 = { 14 }; |
192 extern DwVfpRegister d15; | 191 const DwVfpRegister d15 = { 15 }; |
193 | 192 |
194 | 193 |
195 // Coprocessor register | 194 // Coprocessor register |
196 struct CRegister { | 195 struct CRegister { |
197 bool is_valid() const { return 0 <= code_ && code_ < 16; } | 196 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
198 bool is(CRegister creg) const { return code_ == creg.code_; } | 197 bool is(CRegister creg) const { return code_ == creg.code_; } |
199 int code() const { | 198 int code() const { |
200 ASSERT(is_valid()); | 199 ASSERT(is_valid()); |
201 return code_; | 200 return code_; |
202 } | 201 } |
203 int bit() const { | 202 int bit() const { |
204 ASSERT(is_valid()); | 203 ASSERT(is_valid()); |
205 return 1 << code_; | 204 return 1 << code_; |
206 } | 205 } |
207 | 206 |
208 // Unfortunately we can't make this private in a struct. | 207 // Unfortunately we can't make this private in a struct. |
209 int code_; | 208 int code_; |
210 }; | 209 }; |
211 | 210 |
212 | 211 |
213 extern CRegister no_creg; | 212 const CRegister no_creg = { -1 }; |
214 extern CRegister cr0; | 213 |
215 extern CRegister cr1; | 214 const CRegister cr0 = { 0 }; |
216 extern CRegister cr2; | 215 const CRegister cr1 = { 1 }; |
217 extern CRegister cr3; | 216 const CRegister cr2 = { 2 }; |
218 extern CRegister cr4; | 217 const CRegister cr3 = { 3 }; |
219 extern CRegister cr5; | 218 const CRegister cr4 = { 4 }; |
220 extern CRegister cr6; | 219 const CRegister cr5 = { 5 }; |
221 extern CRegister cr7; | 220 const CRegister cr6 = { 6 }; |
222 extern CRegister cr8; | 221 const CRegister cr7 = { 7 }; |
223 extern CRegister cr9; | 222 const CRegister cr8 = { 8 }; |
224 extern CRegister cr10; | 223 const CRegister cr9 = { 9 }; |
225 extern CRegister cr11; | 224 const CRegister cr10 = { 10 }; |
226 extern CRegister cr12; | 225 const CRegister cr11 = { 11 }; |
227 extern CRegister cr13; | 226 const CRegister cr12 = { 12 }; |
228 extern CRegister cr14; | 227 const CRegister cr13 = { 13 }; |
229 extern CRegister cr15; | 228 const CRegister cr14 = { 14 }; |
| 229 const CRegister cr15 = { 15 }; |
230 | 230 |
231 | 231 |
232 // Coprocessor number | 232 // Coprocessor number |
233 enum Coprocessor { | 233 enum Coprocessor { |
234 p0 = 0, | 234 p0 = 0, |
235 p1 = 1, | 235 p1 = 1, |
236 p2 = 2, | 236 p2 = 2, |
237 p3 = 3, | 237 p3 = 3, |
238 p4 = 4, | 238 p4 = 4, |
239 p5 = 5, | 239 p5 = 5, |
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1027 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 1027 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
1028 | 1028 |
1029 friend class RegExpMacroAssemblerARM; | 1029 friend class RegExpMacroAssemblerARM; |
1030 friend class RelocInfo; | 1030 friend class RelocInfo; |
1031 friend class CodePatcher; | 1031 friend class CodePatcher; |
1032 }; | 1032 }; |
1033 | 1033 |
1034 } } // namespace v8::internal | 1034 } } // namespace v8::internal |
1035 | 1035 |
1036 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1036 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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