Add the SDRAM parameter header file.

nvboot_bct.h

 /**
  * Copyright (c) 2011 NVIDIA Corporation.  All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 
 #ifndef INCLUDED_NVBOOT_BCT_H
 #define INCLUDED_NVBOOT_BCT_H
 
 #include <sys/types.h>
+#include "nvboot_sdram_param.h"
 
 /**
  * Defines the number of 32-bit words in the customer_data area of the BCT.
  */
 #define NVBOOT_BCT_CUSTOMER_DATA_WORDS 298
 
 /**
  * Defines the number of bytes in the customer_data area of the BCT.
  */
 #define NVBOOT_BCT_CUSTOMER_DATA_SIZE \
                 (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4)
 
 /**
  * Defines the number of bytes in the reserved area of the BCT.
  */
 #define NVBOOT_BCT_RESERVED_SIZE       3
 
 /**
  * Defines the maximum number of bootloader descriptions in the BCT.
  */
 #define NVBOOT_MAX_BOOTLOADERS         4
 
-#define NVBOOT_BCT_USED_DATA_SIZE       2052
-
 /**
  * Defines the maximum number of device parameter sets in the BCT.
  * The value must be equal to (1 << # of device straps)
  */
 #define NVBOOT_BCT_MAX_PARAM_SETS      4
 
 /**
+ * Defines the maximum number of SDRAM parameter sets in the BCT.
+ * The value must be equal to (1 << # of SDRAM straps)
+ */
+#define NVBOOT_BCT_MAX_SDRAM_SETS      4
+
+/**
  * Defines the number of entries (bits) in the bad block table.
  * The consequences of changing its value are as follows.  Using P as the
  * # of physical blocks in the boot loader and B as the value of this
  * constant:
  *    B > P: There will be unused storage in the bad block table.
  *    B < P: The virtual block size will be greater than the physical block
  *           size, so the granularity of the bad block table will be less than
  *           one bit per physical block.
  *
  * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one
@@ skipping 24 matching lines @@
 enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4};
 
 /**
  * Defines the storage for a hash value (128 bits).
  */
 typedef struct nvboot_hash_rec
 {
         u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH];
 } nvboot_hash;
 
+/// Defines the params that can be configured for NAND devices.
+typedef struct nvboot_nand_params_rec{
+        /**
+         * Specifies the clock divider for the PLL_P 432MHz source.
+         * If it is set to 18, then clock source to Nand controller is
+         * 432 / 18 = 24MHz.
+         */
+        u_int8_t clock_divider;
+
+        /// Specifies the value to be programmed to Nand Timing Register 1
+        u_int32_t nand_timing;
+
+        /// Specifies the value to be programmed to Nand Timing Register 2
+        u_int32_t nand_timing2;
+
+        /// Specifies the block size in log2 bytes
+        u_int8_t block_size_log2;
+
+        /// Specifies the page size in log2 bytes
+        u_int8_t page_size_log2;
+} nvboot_nand_params;
+
 /// Defines various data widths supported.
 typedef enum
 {
         /**
          * Specifies a 1 bit interface to eMMC.
          * Note that 1-bit data width is only for the driver's internal use.
          * Fuses doesn't provide option to select 1-bit data width.
          * The driver selects 1-bit internally based on need.
          * It is used for reading Extended CSD and when the power class
          * requirements of a card for 4-bit or 8-bit transfers are not
@@ skipping 24 matching lines @@
         /// Specifies the data bus width. Supported data widths are 4/8 bits.
         nvboot_sdmmc_data_width data_width;
 
         /** 
          * Max Power class supported by the target board.
          * The driver determines the best data width and clock frequency
          * supported within the power class range (0 to Max) if the selected
          * data width cannot be used at the chosen clock frequency.
          */
         u_int8_t max_power_class_supported;
-        u_int32_t reserved;
 } nvboot_sdmmc_params;
 
 typedef enum 
 {
         /// Specifies SPI clock source to be PLLP.
         nvboot_spi_clock_source_pllp_out0 = 0,
 
         /// Specifies SPI clock source to be PLLC.
         nvboot_spi_clock_source_pllc_out0,
 
@@ skipping 35 matching lines @@
          * NV_FALSE specifies a NORMAL_READ Command
          * NV_TRUE  specifies a FAST_READ   Command
          */
         u_int8_t read_command_type_fast;
 } nvboot_spiflash_params;
 
 /**
 * Defines the union of the parameters required by each device.
 */
 typedef union{
+        /// Specifies optimized parameters for NAND
+        nvboot_nand_params nand_params;
         /// Specifies optimized parameters for eMMC and eSD
         nvboot_sdmmc_params sdmmc_params;
         /// Specifies optimized parameters for SPI NOR
         nvboot_spiflash_params spiflash_params;
 } nvboot_dev_params;
 
 /**
  * Identifies the types of devices from which the system booted.
  * Used to identify primary and secondary boot devices.
  * @note These no longer match the fuse API device values (for
  * backward compatibility with AP15).
  */
 typedef enum
 {
         /// Specifies a default (unset) value.
         nvboot_dev_type_none = 0,
 
+        /// Specifies NAND.
+        nvboot_dev_type_nand,
+
         /// Specifies SPI NOR.
         nvboot_dev_type_spi = 3,
 
         /// Specifies SDMMC (either eMMC or eSD).
         nvboot_dev_type_sdmmc,
 
         nvboot_dev_type_max,
 
         /// Ignore -- Forces compilers to make 32-bit enums.
         nvboot_dev_type_force32 = 0x7FFFFFFF
@@ skipping 40 matching lines @@
 {
         nvboot_hash crypto_hash;
         nvboot_hash random_aes_blk;
         u_int32_t boot_data_version;
         u_int32_t block_size_log2;
         u_int32_t page_size_log2;
         u_int32_t partition_size;
         u_int32_t num_param_sets;
         nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS];
         nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS];
-        u_int8_t bct_used_data[NVBOOT_BCT_USED_DATA_SIZE];
+        u_int32_t num_sdram_sets;
+        nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS];
         nvboot_badblock_table badblock_table;
         u_int32_t bootloader_used;
         nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
         u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE];
         u_int8_t enable_fail_back;
         u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE];
 } nvboot_config_table;
 
-/** @} */
 #endif /* #ifndef INCLUDED_NVBOOT_BCT_H */