Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(5)

Side by Side Diff: src/arm/simulator-arm.cc

Issue 6594009: Implement int32 TypeRecordingBinaryOp on ARM. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
OLDNEW
1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 2536 matching lines...) Expand 10 before | Expand all | Expand 10 after
2547 set_d_register_from_double(vd, dd_value); 2547 set_d_register_from_double(vd, dd_value);
2548 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) { 2548 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
2549 // vdiv 2549 // vdiv
2550 if (instr->SzValue() != 0x1) { 2550 if (instr->SzValue() != 0x1) {
2551 UNREACHABLE(); // Not used by V8. 2551 UNREACHABLE(); // Not used by V8.
2552 } 2552 }
2553 2553
2554 double dn_value = get_double_from_d_register(vn); 2554 double dn_value = get_double_from_d_register(vn);
2555 double dm_value = get_double_from_d_register(vm); 2555 double dm_value = get_double_from_d_register(vm);
2556 double dd_value = dn_value / dm_value; 2556 double dd_value = dn_value / dm_value;
2557 div_zero_vfp_flag_ = (dm_value == 0);
2557 set_d_register_from_double(vd, dd_value); 2558 set_d_register_from_double(vd, dd_value);
2558 } else { 2559 } else {
2559 UNIMPLEMENTED(); // Not used by V8. 2560 UNIMPLEMENTED(); // Not used by V8.
2560 } 2561 }
2561 } else { 2562 } else {
2562 if ((instr->VCValue() == 0x0) && 2563 if ((instr->VCValue() == 0x0) &&
2563 (instr->VAValue() == 0x0)) { 2564 (instr->VAValue() == 0x0)) {
2564 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); 2565 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
2565 } else if ((instr->VLValue() == 0x1) && 2566 } else if ((instr->VLValue() == 0x1) &&
2566 (instr->VCValue() == 0x0) && 2567 (instr->VCValue() == 0x0) &&
(...skipping 214 matching lines...) Expand 10 before | Expand all | Expand 10 after
2781 bool double_precision = (src_precision == kDoublePrecision); 2782 bool double_precision = (src_precision == kDoublePrecision);
2782 2783
2783 double val = double_precision ? get_double_from_d_register(src) 2784 double val = double_precision ? get_double_from_d_register(src)
2784 : get_float_from_s_register(src); 2785 : get_float_from_s_register(src);
2785 2786
2786 int temp = unsigned_integer ? static_cast<uint32_t>(val) 2787 int temp = unsigned_integer ? static_cast<uint32_t>(val)
2787 : static_cast<int32_t>(val); 2788 : static_cast<int32_t>(val);
2788 2789
2789 inv_op_vfp_flag_ = get_inv_op_vfp_flag(mode, val, unsigned_integer); 2790 inv_op_vfp_flag_ = get_inv_op_vfp_flag(mode, val, unsigned_integer);
2790 2791
2792 double abs_diff =
2793 unsigned_integer ? fabs(val - static_cast<uint32_t>(temp))
2794 : fabs(val - temp);
2795
2796 inexact_vfp_flag_ = (abs_diff != 0);
2797
2791 if (inv_op_vfp_flag_) { 2798 if (inv_op_vfp_flag_) {
2792 temp = VFPConversionSaturate(val, unsigned_integer); 2799 temp = VFPConversionSaturate(val, unsigned_integer);
2793 } else { 2800 } else {
2794 switch (mode) { 2801 switch (mode) {
2795 case RN: { 2802 case RN: {
2796 double abs_diff =
2797 unsigned_integer ? fabs(val - static_cast<uint32_t>(temp))
2798 : fabs(val - temp);
2799 int val_sign = (val > 0) ? 1 : -1; 2803 int val_sign = (val > 0) ? 1 : -1;
2800 if (abs_diff > 0.5) { 2804 if (abs_diff > 0.5) {
2801 temp += val_sign; 2805 temp += val_sign;
2802 } else if (abs_diff == 0.5) { 2806 } else if (abs_diff == 0.5) {
2803 // Round to even if exactly halfway. 2807 // Round to even if exactly halfway.
2804 temp = ((temp % 2) == 0) ? temp : temp + val_sign; 2808 temp = ((temp % 2) == 0) ? temp : temp + val_sign;
2805 } 2809 }
2806 break; 2810 break;
2807 } 2811 }
2808 2812
(...skipping 333 matching lines...) Expand 10 before | Expand all | Expand 10 after
3142 uintptr_t address = *stack_slot; 3146 uintptr_t address = *stack_slot;
3143 set_register(sp, current_sp + sizeof(uintptr_t)); 3147 set_register(sp, current_sp + sizeof(uintptr_t));
3144 return address; 3148 return address;
3145 } 3149 }
3146 3150
3147 } } // namespace v8::internal 3151 } } // namespace v8::internal
3148 3152
3149 #endif // USE_SIMULATOR 3153 #endif // USE_SIMULATOR
3150 3154
3151 #endif // V8_TARGET_ARCH_ARM 3155 #endif // V8_TARGET_ARCH_ARM
OLDNEW
« src/arm/macro-assembler-arm.cc ('K') | « src/arm/macro-assembler-arm.cc ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698