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Side by Side Diff: src/arm/macro-assembler-arm.h

Issue 6594009: Implement int32 TypeRecordingBinaryOp on ARM. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 9 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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114 Register scratch = no_reg, 114 Register scratch = no_reg,
115 Condition cond = al); 115 Condition cond = al);
116 116
117 117
118 void And(Register dst, Register src1, const Operand& src2, 118 void And(Register dst, Register src1, const Operand& src2,
119 Condition cond = al); 119 Condition cond = al);
120 void Ubfx(Register dst, Register src, int lsb, int width, 120 void Ubfx(Register dst, Register src, int lsb, int width,
121 Condition cond = al); 121 Condition cond = al);
122 void Sbfx(Register dst, Register src, int lsb, int width, 122 void Sbfx(Register dst, Register src, int lsb, int width,
123 Condition cond = al); 123 Condition cond = al);
124 // The scratch register is not used for ARMv7.
125 // scratch can be the same register as src (in which case it is trashed), but
126 // not the same as dst.
Søren Thygesen Gjesse 2011/02/28 09:54:32 not -> but not
Søren Thygesen Gjesse 2011/03/02 09:33:08 The but was there in the first place.
127 void Bfi(Register dst,
128 Register src,
129 Register scratch,
130 int lsb,
131 int width,
132 Condition cond = al);
124 void Bfc(Register dst, int lsb, int width, Condition cond = al); 133 void Bfc(Register dst, int lsb, int width, Condition cond = al);
125 void Usat(Register dst, int satpos, const Operand& src, 134 void Usat(Register dst, int satpos, const Operand& src,
126 Condition cond = al); 135 Condition cond = al);
127 136
128 void Call(Label* target); 137 void Call(Label* target);
129 void Move(Register dst, Handle<Object> value); 138 void Move(Register dst, Handle<Object> value);
130 // May do nothing if the registers are identical. 139 // May do nothing if the registers are identical.
131 void Move(Register dst, Register src); 140 void Move(Register dst, Register src);
132 // Jumps to the label at the index given by the Smi in "index". 141 // Jumps to the label at the index given by the Smi in "index".
133 void SmiJumpTable(Register index, Vector<Label*> targets); 142 void SmiJumpTable(Register index, Vector<Label*> targets);
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227 } else { 236 } else {
228 stm(db_w, sp, src1.bit() | src2.bit(), cond); 237 stm(db_w, sp, src1.bit() | src2.bit(), cond);
229 Push(src3, src4, cond); 238 Push(src3, src4, cond);
230 } 239 }
231 } else { 240 } else {
232 str(src1, MemOperand(sp, 4, NegPreIndex), cond); 241 str(src1, MemOperand(sp, 4, NegPreIndex), cond);
233 Push(src2, src3, src4, cond); 242 Push(src2, src3, src4, cond);
234 } 243 }
235 } 244 }
236 245
246 // Pop two registers. Pops rightmost register first (from lower address).
247 void Pop(Register src1, Register src2, Condition cond = al) {
248 ASSERT(!src1.is(src2));
249 if (src1.code() > src2.code()) {
250 ldm(ia_w, sp, src1.bit() | src2.bit(), cond);
251 } else {
252 ldr(src2, MemOperand(sp, 4, PostIndex), cond);
253 ldr(src1, MemOperand(sp, 4, PostIndex), cond);
254 }
255 }
256
237 // Push and pop the registers that can hold pointers, as defined by the 257 // Push and pop the registers that can hold pointers, as defined by the
238 // RegList constant kSafepointSavedRegisters. 258 // RegList constant kSafepointSavedRegisters.
239 void PushSafepointRegisters(); 259 void PushSafepointRegisters();
240 void PopSafepointRegisters(); 260 void PopSafepointRegisters();
241 void PushSafepointRegistersAndDoubles(); 261 void PushSafepointRegistersAndDoubles();
242 void PopSafepointRegistersAndDoubles(); 262 void PopSafepointRegistersAndDoubles();
243 // Store value in register src in the safepoint stack slot for 263 // Store value in register src in the safepoint stack slot for
244 // register dst. 264 // register dst.
245 void StoreToSafepointRegisterSlot(Register src, Register dst); 265 void StoreToSafepointRegisterSlot(Register src, Register dst);
246 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst); 266 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst);
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606 // dest. If the HeapNumber does not fit into a 32bits signed integer branch 626 // dest. If the HeapNumber does not fit into a 32bits signed integer branch
607 // to not_int32 label. If VFP3 is available double_scratch is used but not 627 // to not_int32 label. If VFP3 is available double_scratch is used but not
608 // scratch2. 628 // scratch2.
609 void ConvertToInt32(Register source, 629 void ConvertToInt32(Register source,
610 Register dest, 630 Register dest,
611 Register scratch, 631 Register scratch,
612 Register scratch2, 632 Register scratch2,
613 DwVfpRegister double_scratch, 633 DwVfpRegister double_scratch,
614 Label *not_int32); 634 Label *not_int32);
615 635
636 // Truncates a double using a specific rounding mode.
637 // Clears the z flag (ne condition) if an overflow occurs.
638 // If exact_conversion is true, the z flag is also cleared if the conversion
639 // was inexact, ie. if the double value could not be converted exactly
640 // to a 32bit integer.
641 void EmitVFPTruncate(VFPRoundingMode rounding_mode,
642 SwVfpRegister result,
643 DwVfpRegister double_input,
644 Register scratch1,
645 Register scratch2,
646 CheckForInexactConversion check
647 = kDontCheckForInexactConversion);
648
616 // Count leading zeros in a 32 bit word. On ARM5 and later it uses the clz 649 // Count leading zeros in a 32 bit word. On ARM5 and later it uses the clz
617 // instruction. On pre-ARM5 hardware this routine gives the wrong answer 650 // instruction. On pre-ARM5 hardware this routine gives the wrong answer
618 // for 0 (31 instead of 32). Source and scratch can be the same in which case 651 // for 0 (31 instead of 32). Source and scratch can be the same in which case
619 // the source is clobbered. Source and zeros can also be the same in which 652 // the source is clobbered. Source and zeros can also be the same in which
620 // case scratch should be a different register. 653 // case scratch should be a different register.
621 void CountLeadingZeros(Register zeros, 654 void CountLeadingZeros(Register zeros,
622 Register source, 655 Register source,
623 Register scratch); 656 Register scratch);
624 657
625 // --------------------------------------------------------------------------- 658 // ---------------------------------------------------------------------------
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965 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 998 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
966 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 999 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
967 #else 1000 #else
968 #define ACCESS_MASM(masm) masm-> 1001 #define ACCESS_MASM(masm) masm->
969 #endif 1002 #endif
970 1003
971 1004
972 } } // namespace v8::internal 1005 } } // namespace v8::internal
973 1006
974 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_ 1007 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_
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