| OLD | NEW |
| 1 /* | 1 /* |
| 2 * Fifo-attached Serial Interface (FSI) support for SH7724 | 2 * Fifo-attached Serial Interface (FSI) support for SH7724 |
| 3 * | 3 * |
| 4 * Copyright (C) 2009 Renesas Solutions Corp. | 4 * Copyright (C) 2009 Renesas Solutions Corp. |
| 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> | 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> |
| 6 * | 6 * |
| 7 * Based on ssi.c | 7 * Based on ssi.c |
| 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> |
| 9 * | 9 * |
| 10 * This program is free software; you can redistribute it and/or modify | 10 * This program is free software; you can redistribute it and/or modify |
| 11 * it under the terms of the GNU General Public License version 2 as | 11 * it under the terms of the GNU General Public License version 2 as |
| 12 * published by the Free Software Foundation. | 12 * published by the Free Software Foundation. |
| 13 */ | 13 */ |
| 14 | 14 |
| 15 #include <linux/delay.h> | 15 #include <linux/delay.h> |
| 16 #include <linux/pm_runtime.h> | 16 #include <linux/pm_runtime.h> |
| 17 #include <linux/io.h> | 17 #include <linux/io.h> |
| 18 #include <linux/slab.h> | 18 #include <linux/slab.h> |
| 19 #include <sound/soc.h> | 19 #include <sound/soc.h> |
| 20 #include <sound/sh_fsi.h> | 20 #include <sound/sh_fsi.h> |
| 21 | 21 |
| 22 #define DO_FMT» » 0x0000 | 22 /* PortA/PortB register */ |
| 23 #define DOFF_CTL» 0x0004 | 23 #define REG_DO_FMT» 0x0000 |
| 24 #define DOFF_ST»» 0x0008 | 24 #define REG_DOFF_CTL» 0x0004 |
| 25 #define DI_FMT» » 0x000C | 25 #define REG_DOFF_ST» 0x0008 |
| 26 #define DIFF_CTL» 0x0010 | 26 #define REG_DI_FMT» 0x000C |
| 27 #define DIFF_ST»» 0x0014 | 27 #define REG_DIFF_CTL» 0x0010 |
| 28 #define CKG1» » 0x0018 | 28 #define REG_DIFF_ST» 0x0014 |
| 29 #define CKG2» » 0x001C | 29 #define REG_CKG1» 0x0018 |
| 30 #define DIDT» » 0x0020 | 30 #define REG_CKG2» 0x001C |
| 31 #define DODT» » 0x0024 | 31 #define REG_DIDT» 0x0020 |
| 32 #define MUTE_ST»» 0x0028 | 32 #define REG_DODT» 0x0024 |
| 33 #define OUT_SEL»» 0x0030 | 33 #define REG_MUTE_ST» 0x0028 |
| 34 #define REG_END»» OUT_SEL | 34 #define REG_OUT_SEL» 0x0030 |
| 35 | 35 |
| 36 /* master register */ |
| 37 #define MST_CLK_RST 0x0210 |
| 38 #define MST_SOFT_RST 0x0214 |
| 39 #define MST_FIFO_SZ 0x0218 |
| 40 |
| 41 /* core register (depend on FSI version) */ |
| 36 #define A_MST_CTLR 0x0180 | 42 #define A_MST_CTLR 0x0180 |
| 37 #define B_MST_CTLR 0x01A0 | 43 #define B_MST_CTLR 0x01A0 |
| 38 #define CPU_INT_ST 0x01F4 | 44 #define CPU_INT_ST 0x01F4 |
| 39 #define CPU_IEMSK 0x01F8 | 45 #define CPU_IEMSK 0x01F8 |
| 40 #define CPU_IMSK 0x01FC | 46 #define CPU_IMSK 0x01FC |
| 41 #define INT_ST 0x0200 | 47 #define INT_ST 0x0200 |
| 42 #define IEMSK 0x0204 | 48 #define IEMSK 0x0204 |
| 43 #define IMSK 0x0208 | 49 #define IMSK 0x0208 |
| 44 #define MUTE 0x020C | |
| 45 #define CLK_RST 0x0210 | |
| 46 #define SOFT_RST 0x0214 | |
| 47 #define FIFO_SZ 0x0218 | |
| 48 #define MREG_START A_MST_CTLR | |
| 49 #define MREG_END FIFO_SZ | |
| 50 | 50 |
| 51 /* DO_FMT */ | 51 /* DO_FMT */ |
| 52 /* DI_FMT */ | 52 /* DI_FMT */ |
| 53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
| 54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ |
| 55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ |
| 56 |
| 57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ |
| 58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ |
| 59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ |
| 60 |
| 53 #define CR_MONO (0x0 << 4) | 61 #define CR_MONO (0x0 << 4) |
| 54 #define CR_MONO_D (0x1 << 4) | 62 #define CR_MONO_D (0x1 << 4) |
| 55 #define CR_PCM (0x2 << 4) | 63 #define CR_PCM (0x2 << 4) |
| 56 #define CR_I2S (0x3 << 4) | 64 #define CR_I2S (0x3 << 4) |
| 57 #define CR_TDM (0x4 << 4) | 65 #define CR_TDM (0x4 << 4) |
| 58 #define CR_TDM_D (0x5 << 4) | 66 #define CR_TDM_D (0x5 << 4) |
| 59 #define CR_SPDIF 0x00100120 | |
| 60 | 67 |
| 61 /* DOFF_CTL */ | 68 /* DOFF_CTL */ |
| 62 /* DIFF_CTL */ | 69 /* DIFF_CTL */ |
| 63 #define IRQ_HALF 0x00100000 | 70 #define IRQ_HALF 0x00100000 |
| 64 #define FIFO_CLR 0x00000001 | 71 #define FIFO_CLR 0x00000001 |
| 65 | 72 |
| 66 /* DOFF_ST */ | 73 /* DOFF_ST */ |
| 67 #define ERR_OVER 0x00000010 | 74 #define ERR_OVER 0x00000010 |
| 68 #define ERR_UNDER 0x00000001 | 75 #define ERR_UNDER 0x00000001 |
| 69 #define ST_ERR (ERR_OVER | ERR_UNDER) | 76 #define ST_ERR (ERR_OVER | ERR_UNDER) |
| 70 | 77 |
| 71 /* CKG1 */ | 78 /* CKG1 */ |
| 72 #define ACKMD_MASK 0x00007000 | 79 #define ACKMD_MASK 0x00007000 |
| 73 #define BPFMD_MASK 0x00000700 | 80 #define BPFMD_MASK 0x00000700 |
| 81 #define DIMD (1 << 4) |
| 82 #define DOMD (1 << 0) |
| 74 | 83 |
| 75 /* A/B MST_CTLR */ | 84 /* A/B MST_CTLR */ |
| 76 #define BP (1 << 4) /* Fix the signal of Biphase output */ | 85 #define BP (1 << 4) /* Fix the signal of Biphase output */ |
| 77 #define SE (1 << 0) /* Fix the master clock */ | 86 #define SE (1 << 0) /* Fix the master clock */ |
| 78 | 87 |
| 79 /* CLK_RST */ | 88 /* CLK_RST */ |
| 80 #define B_CLK 0x00000010 | 89 #define B_CLK 0x00000010 |
| 81 #define A_CLK 0x00000001 | 90 #define A_CLK 0x00000001 |
| 82 | 91 |
| 83 /* IO SHIFT / MACRO */ | 92 /* IO SHIFT / MACRO */ |
| 84 #define BI_SHIFT 12 | 93 #define BI_SHIFT 12 |
| 85 #define BO_SHIFT 8 | 94 #define BO_SHIFT 8 |
| 86 #define AI_SHIFT 4 | 95 #define AI_SHIFT 4 |
| 87 #define AO_SHIFT 0 | 96 #define AO_SHIFT 0 |
| 88 #define AB_IO(param, shift) (param << shift) | 97 #define AB_IO(param, shift) (param << shift) |
| 89 | 98 |
| 90 /* SOFT_RST */ | 99 /* SOFT_RST */ |
| 91 #define PBSR (1 << 12) /* Port B Software Reset */ | 100 #define PBSR (1 << 12) /* Port B Software Reset */ |
| 92 #define PASR (1 << 8) /* Port A Software Reset */ | 101 #define PASR (1 << 8) /* Port A Software Reset */ |
| 93 #define IR (1 << 4) /* Interrupt Reset */ | 102 #define IR (1 << 4) /* Interrupt Reset */ |
| 94 #define FSISR (1 << 0) /* Software Reset */ | 103 #define FSISR (1 << 0) /* Software Reset */ |
| 95 | 104 |
| 105 /* OUT_SEL (FSI2) */ |
| 106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ |
| 107 /* 1: Biphase and serial */ |
| 108 |
| 96 /* FIFO_SZ */ | 109 /* FIFO_SZ */ |
| 97 #define FIFO_SZ_MASK 0x7 | 110 #define FIFO_SZ_MASK 0x7 |
| 98 | 111 |
| 99 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 | 112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
| 100 | 113 |
| 101 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | 114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) |
| 102 | 115 |
| 116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int ena
ble); |
| 117 |
| 103 /* | 118 /* |
| 104 * FSI driver use below type name for variable | 119 * FSI driver use below type name for variable |
| 105 * | 120 * |
| 106 * xxx_len : data length | 121 * xxx_len : data length |
| 107 * xxx_width : data width | 122 * xxx_width : data width |
| 108 * xxx_offset : data offset | 123 * xxx_offset : data offset |
| 109 * xxx_num : number of data | 124 * xxx_num : number of data |
| 110 */ | 125 */ |
| 111 | 126 |
| 112 /* | 127 /* |
| 113 * struct | 128 * struct |
| 114 */ | 129 */ |
| 115 | 130 |
| 116 struct fsi_stream { | 131 struct fsi_stream { |
| 117 struct snd_pcm_substream *substream; | 132 struct snd_pcm_substream *substream; |
| 118 | 133 |
| 119 int fifo_max_num; | 134 int fifo_max_num; |
| 120 int chan_num; | |
| 121 | 135 |
| 122 int buff_offset; | 136 int buff_offset; |
| 123 int buff_len; | 137 int buff_len; |
| 124 int period_len; | 138 int period_len; |
| 125 int period_num; | 139 int period_num; |
| 140 |
| 141 int uerr_num; |
| 142 int oerr_num; |
| 126 }; | 143 }; |
| 127 | 144 |
| 128 struct fsi_priv { | 145 struct fsi_priv { |
| 129 void __iomem *base; | 146 void __iomem *base; |
| 130 struct fsi_master *master; | 147 struct fsi_master *master; |
| 131 | 148 |
| 149 int chan_num; |
| 132 struct fsi_stream playback; | 150 struct fsi_stream playback; |
| 133 struct fsi_stream capture; | 151 struct fsi_stream capture; |
| 134 | 152 |
| 135 long rate; | 153 long rate; |
| 136 | |
| 137 u32 mst_ctrl; | |
| 138 }; | 154 }; |
| 139 | 155 |
| 140 struct fsi_core { | 156 struct fsi_core { |
| 141 int ver; | 157 int ver; |
| 142 | 158 |
| 143 u32 int_st; | 159 u32 int_st; |
| 144 u32 iemsk; | 160 u32 iemsk; |
| 145 u32 imsk; | 161 u32 imsk; |
| 162 u32 a_mclk; |
| 163 u32 b_mclk; |
| 146 }; | 164 }; |
| 147 | 165 |
| 148 struct fsi_master { | 166 struct fsi_master { |
| 149 void __iomem *base; | 167 void __iomem *base; |
| 150 int irq; | 168 int irq; |
| 151 struct fsi_priv fsia; | 169 struct fsi_priv fsia; |
| 152 struct fsi_priv fsib; | 170 struct fsi_priv fsib; |
| 153 struct fsi_core *core; | 171 struct fsi_core *core; |
| 154 struct sh_fsi_platform_info *info; | 172 struct sh_fsi_platform_info *info; |
| 155 spinlock_t lock; | 173 spinlock_t lock; |
| (...skipping 19 matching lines...) Expand all Loading... |
| 175 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) | 193 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
| 176 { | 194 { |
| 177 u32 val = __fsi_reg_read(reg); | 195 u32 val = __fsi_reg_read(reg); |
| 178 | 196 |
| 179 val &= ~mask; | 197 val &= ~mask; |
| 180 val |= data & mask; | 198 val |= data & mask; |
| 181 | 199 |
| 182 __fsi_reg_write(reg, val); | 200 __fsi_reg_write(reg, val); |
| 183 } | 201 } |
| 184 | 202 |
| 185 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) | 203 #define fsi_reg_write(p, r, d)\ |
| 186 { | 204 » __fsi_reg_write((u32)(p->base + REG_##r), d) |
| 187 » if (reg > REG_END) { | |
| 188 » » pr_err("fsi: register access err (%s)\n", __func__); | |
| 189 » » return; | |
| 190 » } | |
| 191 | 205 |
| 192 » __fsi_reg_write((u32)(fsi->base + reg), data); | 206 #define fsi_reg_read(p, r)\ |
| 193 } | 207 » __fsi_reg_read((u32)(p->base + REG_##r)) |
| 194 | 208 |
| 195 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | 209 #define fsi_reg_mask_set(p, r, m, d)\ |
| 196 { | 210 » __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) |
| 197 » if (reg > REG_END) { | |
| 198 » » pr_err("fsi: register access err (%s)\n", __func__); | |
| 199 » » return 0; | |
| 200 » } | |
| 201 | 211 |
| 202 » return __fsi_reg_read((u32)(fsi->base + reg)); | 212 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
| 203 } | 213 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) |
| 204 | 214 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) |
| 205 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) | |
| 206 { | |
| 207 » if (reg > REG_END) { | |
| 208 » » pr_err("fsi: register access err (%s)\n", __func__); | |
| 209 » » return; | |
| 210 » } | |
| 211 | |
| 212 » __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); | |
| 213 } | |
| 214 | |
| 215 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) | |
| 216 { | |
| 217 » unsigned long flags; | |
| 218 | |
| 219 » if ((reg < MREG_START) || | |
| 220 » (reg > MREG_END)) { | |
| 221 » » pr_err("fsi: register access err (%s)\n", __func__); | |
| 222 » » return; | |
| 223 » } | |
| 224 | |
| 225 » spin_lock_irqsave(&master->lock, flags); | |
| 226 » __fsi_reg_write((u32)(master->base + reg), data); | |
| 227 » spin_unlock_irqrestore(&master->lock, flags); | |
| 228 } | |
| 229 | |
| 230 static u32 fsi_master_read(struct fsi_master *master, u32 reg) | |
| 231 { | 215 { |
| 232 u32 ret; | 216 u32 ret; |
| 233 unsigned long flags; | 217 unsigned long flags; |
| 234 | 218 |
| 235 if ((reg < MREG_START) || | |
| 236 (reg > MREG_END)) { | |
| 237 pr_err("fsi: register access err (%s)\n", __func__); | |
| 238 return 0; | |
| 239 } | |
| 240 | |
| 241 spin_lock_irqsave(&master->lock, flags); | 219 spin_lock_irqsave(&master->lock, flags); |
| 242 ret = __fsi_reg_read((u32)(master->base + reg)); | 220 ret = __fsi_reg_read((u32)(master->base + reg)); |
| 243 spin_unlock_irqrestore(&master->lock, flags); | 221 spin_unlock_irqrestore(&master->lock, flags); |
| 244 | 222 |
| 245 return ret; | 223 return ret; |
| 246 } | 224 } |
| 247 | 225 |
| 248 static void fsi_master_mask_set(struct fsi_master *master, | 226 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
| 227 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) |
| 228 static void _fsi_master_mask_set(struct fsi_master *master, |
| 249 u32 reg, u32 mask, u32 data) | 229 u32 reg, u32 mask, u32 data) |
| 250 { | 230 { |
| 251 unsigned long flags; | 231 unsigned long flags; |
| 252 | 232 |
| 253 if ((reg < MREG_START) || | |
| 254 (reg > MREG_END)) { | |
| 255 pr_err("fsi: register access err (%s)\n", __func__); | |
| 256 return; | |
| 257 } | |
| 258 | |
| 259 spin_lock_irqsave(&master->lock, flags); | 233 spin_lock_irqsave(&master->lock, flags); |
| 260 __fsi_reg_mask_set((u32)(master->base + reg), mask, data); | 234 __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
| 261 spin_unlock_irqrestore(&master->lock, flags); | 235 spin_unlock_irqrestore(&master->lock, flags); |
| 262 } | 236 } |
| 263 | 237 |
| 264 /* | 238 /* |
| 265 * basic function | 239 * basic function |
| 266 */ | 240 */ |
| 267 | 241 |
| 268 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) | 242 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
| 269 { | 243 { |
| 270 return fsi->master; | 244 return fsi->master; |
| 271 } | 245 } |
| 272 | 246 |
| 273 static int fsi_is_port_a(struct fsi_priv *fsi) | 247 static int fsi_is_port_a(struct fsi_priv *fsi) |
| 274 { | 248 { |
| 275 return fsi->master->base == fsi->base; | 249 return fsi->master->base == fsi->base; |
| 276 } | 250 } |
| 277 | 251 |
| 278 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) | 252 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
| 279 { | 253 { |
| 280 struct snd_soc_pcm_runtime *rtd = substream->private_data; | 254 struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 281 | 255 |
| 282 return rtd->cpu_dai; | 256 return rtd->cpu_dai; |
| 283 } | 257 } |
| 284 | 258 |
| 285 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | 259 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
| 286 { | 260 { |
| 287 struct snd_soc_dai *dai = fsi_get_dai(substream); | |
| 288 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); | 261 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
| 289 | 262 |
| 290 if (dai->id == 0) | 263 if (dai->id == 0) |
| 291 return &master->fsia; | 264 return &master->fsia; |
| 292 else | 265 else |
| 293 return &master->fsib; | 266 return &master->fsib; |
| 294 } | 267 } |
| 295 | 268 |
| 269 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
| 270 { |
| 271 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); |
| 272 } |
| 273 |
| 274 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
| 275 { |
| 276 if (!master->info) |
| 277 return NULL; |
| 278 |
| 279 return master->info->set_rate; |
| 280 } |
| 281 |
| 296 static u32 fsi_get_info_flags(struct fsi_priv *fsi) | 282 static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
| 297 { | 283 { |
| 298 int is_porta = fsi_is_port_a(fsi); | 284 int is_porta = fsi_is_port_a(fsi); |
| 299 struct fsi_master *master = fsi_get_master(fsi); | 285 struct fsi_master *master = fsi_get_master(fsi); |
| 300 | 286 |
| 287 if (!master->info) |
| 288 return 0; |
| 289 |
| 301 return is_porta ? master->info->porta_flags : | 290 return is_porta ? master->info->porta_flags : |
| 302 master->info->portb_flags; | 291 master->info->portb_flags; |
| 303 } | 292 } |
| 304 | 293 |
| 305 static inline int fsi_stream_is_play(int stream) | 294 static inline int fsi_stream_is_play(int stream) |
| 306 { | 295 { |
| 307 return stream == SNDRV_PCM_STREAM_PLAYBACK; | 296 return stream == SNDRV_PCM_STREAM_PLAYBACK; |
| 308 } | 297 } |
| 309 | 298 |
| 310 static inline int fsi_is_play(struct snd_pcm_substream *substream) | 299 static inline int fsi_is_play(struct snd_pcm_substream *substream) |
| 311 { | 300 { |
| 312 return fsi_stream_is_play(substream->stream); | 301 return fsi_stream_is_play(substream->stream); |
| 313 } | 302 } |
| 314 | 303 |
| 315 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | 304 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, |
| 316 int is_play) | 305 int is_play) |
| 317 { | 306 { |
| 318 return is_play ? &fsi->playback : &fsi->capture; | 307 return is_play ? &fsi->playback : &fsi->capture; |
| 319 } | 308 } |
| 320 | 309 |
| 321 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
| 322 { | |
| 323 u32 mode; | |
| 324 u32 flags = fsi_get_info_flags(fsi); | |
| 325 | |
| 326 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
| 327 | |
| 328 /* return | |
| 329 * 1 : master mode | |
| 330 * 0 : slave mode | |
| 331 */ | |
| 332 | |
| 333 return (mode & flags) != mode; | |
| 334 } | |
| 335 | |
| 336 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) | 310 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
| 337 { | 311 { |
| 338 int is_porta = fsi_is_port_a(fsi); | 312 int is_porta = fsi_is_port_a(fsi); |
| 339 u32 shift; | 313 u32 shift; |
| 340 | 314 |
| 341 if (is_porta) | 315 if (is_porta) |
| 342 shift = is_play ? AO_SHIFT : AI_SHIFT; | 316 shift = is_play ? AO_SHIFT : AI_SHIFT; |
| 343 else | 317 else |
| 344 shift = is_play ? BO_SHIFT : BI_SHIFT; | 318 shift = is_play ? BO_SHIFT : BI_SHIFT; |
| 345 | 319 |
| 346 return shift; | 320 return shift; |
| 347 } | 321 } |
| 348 | 322 |
| 349 static void fsi_stream_push(struct fsi_priv *fsi, | 323 static void fsi_stream_push(struct fsi_priv *fsi, |
| 350 int is_play, | 324 int is_play, |
| 351 struct snd_pcm_substream *substream, | 325 struct snd_pcm_substream *substream, |
| 352 u32 buffer_len, | 326 u32 buffer_len, |
| 353 u32 period_len) | 327 u32 period_len) |
| 354 { | 328 { |
| 355 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 329 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| 356 | 330 |
| 357 io->substream = substream; | 331 io->substream = substream; |
| 358 io->buff_len = buffer_len; | 332 io->buff_len = buffer_len; |
| 359 io->buff_offset = 0; | 333 io->buff_offset = 0; |
| 360 io->period_len = period_len; | 334 io->period_len = period_len; |
| 361 io->period_num = 0; | 335 io->period_num = 0; |
| 336 io->oerr_num = -1; /* ignore 1st err */ |
| 337 io->uerr_num = -1; /* ignore 1st err */ |
| 362 } | 338 } |
| 363 | 339 |
| 364 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) | 340 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
| 365 { | 341 { |
| 366 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 342 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| 343 struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
| 344 |
| 345 |
| 346 if (io->oerr_num > 0) |
| 347 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); |
| 348 |
| 349 if (io->uerr_num > 0) |
| 350 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); |
| 367 | 351 |
| 368 io->substream = NULL; | 352 io->substream = NULL; |
| 369 io->buff_len = 0; | 353 io->buff_len = 0; |
| 370 io->buff_offset = 0; | 354 io->buff_offset = 0; |
| 371 io->period_len = 0; | 355 io->period_len = 0; |
| 372 io->period_num = 0; | 356 io->period_num = 0; |
| 357 io->oerr_num = 0; |
| 358 io->uerr_num = 0; |
| 373 } | 359 } |
| 374 | 360 |
| 375 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) | 361 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
| 376 { | 362 { |
| 377 u32 status; | 363 u32 status; |
| 378 u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
| 379 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
| 380 int data_num; | 364 int data_num; |
| 381 | 365 |
| 382 » status = fsi_reg_read(fsi, reg); | 366 » status = is_play ? |
| 367 » » fsi_reg_read(fsi, DOFF_ST) : |
| 368 » » fsi_reg_read(fsi, DIFF_ST); |
| 369 |
| 383 data_num = 0x1ff & (status >> 8); | 370 data_num = 0x1ff & (status >> 8); |
| 384 » data_num *= io->chan_num; | 371 » data_num *= fsi->chan_num; |
| 385 | 372 |
| 386 return data_num; | 373 return data_num; |
| 387 } | 374 } |
| 388 | 375 |
| 389 static int fsi_len2num(int len, int width) | 376 static int fsi_len2num(int len, int width) |
| 390 { | 377 { |
| 391 return len / width; | 378 return len / width; |
| 392 } | 379 } |
| 393 | 380 |
| 394 #define fsi_num2offset(a, b) fsi_num2len(a, b) | 381 #define fsi_num2offset(a, b) fsi_num2len(a, b) |
| 395 static int fsi_num2len(int num, int width) | 382 static int fsi_num2len(int num, int width) |
| 396 { | 383 { |
| 397 return num * width; | 384 return num * width; |
| 398 } | 385 } |
| 399 | 386 |
| 400 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) | 387 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) |
| 401 { | 388 { |
| 402 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 389 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| 403 struct snd_pcm_substream *substream = io->substream; | 390 struct snd_pcm_substream *substream = io->substream; |
| 404 struct snd_pcm_runtime *runtime = substream->runtime; | 391 struct snd_pcm_runtime *runtime = substream->runtime; |
| 405 | 392 |
| 406 » return frames_to_bytes(runtime, 1) / io->chan_num; | 393 » return frames_to_bytes(runtime, 1) / fsi->chan_num; |
| 394 } |
| 395 |
| 396 static void fsi_count_fifo_err(struct fsi_priv *fsi) |
| 397 { |
| 398 » u32 ostatus = fsi_reg_read(fsi, DOFF_ST); |
| 399 » u32 istatus = fsi_reg_read(fsi, DIFF_ST); |
| 400 |
| 401 » if (ostatus & ERR_OVER) |
| 402 » » fsi->playback.oerr_num++; |
| 403 |
| 404 » if (ostatus & ERR_UNDER) |
| 405 » » fsi->playback.uerr_num++; |
| 406 |
| 407 » if (istatus & ERR_OVER) |
| 408 » » fsi->capture.oerr_num++; |
| 409 |
| 410 » if (istatus & ERR_UNDER) |
| 411 » » fsi->capture.uerr_num++; |
| 412 |
| 413 » fsi_reg_write(fsi, DOFF_ST, 0); |
| 414 » fsi_reg_write(fsi, DIFF_ST, 0); |
| 407 } | 415 } |
| 408 | 416 |
| 409 /* | 417 /* |
| 410 * dma function | 418 * dma function |
| 411 */ | 419 */ |
| 412 | 420 |
| 413 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) | 421 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
| 414 { | 422 { |
| 415 int is_play = fsi_stream_is_play(stream); | 423 int is_play = fsi_stream_is_play(stream); |
| 416 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 424 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| (...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 466 | 474 |
| 467 /* | 475 /* |
| 468 * irq function | 476 * irq function |
| 469 */ | 477 */ |
| 470 | 478 |
| 471 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) | 479 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
| 472 { | 480 { |
| 473 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); | 481 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
| 474 struct fsi_master *master = fsi_get_master(fsi); | 482 struct fsi_master *master = fsi_get_master(fsi); |
| 475 | 483 |
| 476 » fsi_master_mask_set(master, master->core->imsk, data, data); | 484 » fsi_core_mask_set(master, imsk, data, data); |
| 477 » fsi_master_mask_set(master, master->core->iemsk, data, data); | 485 » fsi_core_mask_set(master, iemsk, data, data); |
| 478 } | 486 } |
| 479 | 487 |
| 480 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | 488 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) |
| 481 { | 489 { |
| 482 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); | 490 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
| 483 struct fsi_master *master = fsi_get_master(fsi); | 491 struct fsi_master *master = fsi_get_master(fsi); |
| 484 | 492 |
| 485 » fsi_master_mask_set(master, master->core->imsk, data, 0); | 493 » fsi_core_mask_set(master, imsk, data, 0); |
| 486 » fsi_master_mask_set(master, master->core->iemsk, data, 0); | 494 » fsi_core_mask_set(master, iemsk, data, 0); |
| 487 } | 495 } |
| 488 | 496 |
| 489 static u32 fsi_irq_get_status(struct fsi_master *master) | 497 static u32 fsi_irq_get_status(struct fsi_master *master) |
| 490 { | 498 { |
| 491 » return fsi_master_read(master, master->core->int_st); | 499 » return fsi_core_read(master, int_st); |
| 492 } | |
| 493 | |
| 494 static void fsi_irq_clear_all_status(struct fsi_master *master) | |
| 495 { | |
| 496 » fsi_master_write(master, master->core->int_st, 0); | |
| 497 } | 500 } |
| 498 | 501 |
| 499 static void fsi_irq_clear_status(struct fsi_priv *fsi) | 502 static void fsi_irq_clear_status(struct fsi_priv *fsi) |
| 500 { | 503 { |
| 501 u32 data = 0; | 504 u32 data = 0; |
| 502 struct fsi_master *master = fsi_get_master(fsi); | 505 struct fsi_master *master = fsi_get_master(fsi); |
| 503 | 506 |
| 504 data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); | 507 data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
| 505 data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | 508 data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); |
| 506 | 509 |
| 507 /* clear interrupt factor */ | 510 /* clear interrupt factor */ |
| 508 » fsi_master_mask_set(master, master->core->int_st, data, 0); | 511 » fsi_core_mask_set(master, int_st, data, 0); |
| 509 } | 512 } |
| 510 | 513 |
| 511 /* | 514 /* |
| 512 * SPDIF master clock function | 515 * SPDIF master clock function |
| 513 * | 516 * |
| 514 * These functions are used later FSI2 | 517 * These functions are used later FSI2 |
| 515 */ | 518 */ |
| 516 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) | 519 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
| 517 { | 520 { |
| 518 struct fsi_master *master = fsi_get_master(fsi); | 521 struct fsi_master *master = fsi_get_master(fsi); |
| 519 » u32 val = BP | SE; | 522 » u32 mask, val; |
| 520 | 523 |
| 521 if (master->core->ver < 2) { | 524 if (master->core->ver < 2) { |
| 522 pr_err("fsi: register access err (%s)\n", __func__); | 525 pr_err("fsi: register access err (%s)\n", __func__); |
| 523 return; | 526 return; |
| 524 } | 527 } |
| 525 | 528 |
| 526 » if (enable) | 529 » mask = BP | SE; |
| 527 » » fsi_master_mask_set(master, fsi->mst_ctrl, val, val); | 530 » val = enable ? mask : 0; |
| 528 » else | 531 |
| 529 » » fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); | 532 » fsi_is_port_a(fsi) ? |
| 533 » » fsi_core_mask_set(master, a_mclk, mask, val) : |
| 534 » » fsi_core_mask_set(master, b_mclk, mask, val); |
| 530 } | 535 } |
| 531 | 536 |
| 532 /* | 537 /* |
| 533 * ctrl function | 538 * ctrl function |
| 534 */ | 539 */ |
| 535 | 540 |
| 536 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) | 541 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
| 537 { | 542 { |
| 538 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | 543 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); |
| 539 struct fsi_master *master = fsi_get_master(fsi); | 544 struct fsi_master *master = fsi_get_master(fsi); |
| 540 | 545 |
| 541 if (enable) | 546 if (enable) |
| 542 fsi_master_mask_set(master, CLK_RST, val, val); | 547 fsi_master_mask_set(master, CLK_RST, val, val); |
| 543 else | 548 else |
| 544 fsi_master_mask_set(master, CLK_RST, val, 0); | 549 fsi_master_mask_set(master, CLK_RST, val, 0); |
| 545 } | 550 } |
| 546 | 551 |
| 547 static void fsi_fifo_init(struct fsi_priv *fsi, | 552 static void fsi_fifo_init(struct fsi_priv *fsi, |
| 548 int is_play, | 553 int is_play, |
| 549 struct snd_soc_dai *dai) | 554 struct snd_soc_dai *dai) |
| 550 { | 555 { |
| 551 struct fsi_master *master = fsi_get_master(fsi); | 556 struct fsi_master *master = fsi_get_master(fsi); |
| 552 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 557 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| 553 » u32 ctrl, shift, i; | 558 » u32 shift, i; |
| 554 | 559 |
| 555 /* get on-chip RAM capacity */ | 560 /* get on-chip RAM capacity */ |
| 556 shift = fsi_master_read(master, FIFO_SZ); | 561 shift = fsi_master_read(master, FIFO_SZ); |
| 557 shift >>= fsi_get_port_shift(fsi, is_play); | 562 shift >>= fsi_get_port_shift(fsi, is_play); |
| 558 shift &= FIFO_SZ_MASK; | 563 shift &= FIFO_SZ_MASK; |
| 559 io->fifo_max_num = 256 << shift; | 564 io->fifo_max_num = 256 << shift; |
| 560 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); | 565 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); |
| 561 | 566 |
| 562 /* | 567 /* |
| 563 * The maximum number of sample data varies depending | 568 * The maximum number of sample data varies depending |
| 564 * on the number of channels selected for the format. | 569 * on the number of channels selected for the format. |
| 565 * | 570 * |
| 566 * FIFOs are used in 4-channel units in 3-channel mode | 571 * FIFOs are used in 4-channel units in 3-channel mode |
| 567 * and in 8-channel units in 5- to 7-channel mode | 572 * and in 8-channel units in 5- to 7-channel mode |
| 568 * meaning that more FIFOs than the required size of DPRAM | 573 * meaning that more FIFOs than the required size of DPRAM |
| 569 * are used. | 574 * are used. |
| 570 * | 575 * |
| 571 * ex) if 256 words of DP-RAM is connected | 576 * ex) if 256 words of DP-RAM is connected |
| 572 * 1 channel: 256 (256 x 1 = 256) | 577 * 1 channel: 256 (256 x 1 = 256) |
| 573 * 2 channels: 128 (128 x 2 = 256) | 578 * 2 channels: 128 (128 x 2 = 256) |
| 574 * 3 channels: 64 ( 64 x 3 = 192) | 579 * 3 channels: 64 ( 64 x 3 = 192) |
| 575 * 4 channels: 64 ( 64 x 4 = 256) | 580 * 4 channels: 64 ( 64 x 4 = 256) |
| 576 * 5 channels: 32 ( 32 x 5 = 160) | 581 * 5 channels: 32 ( 32 x 5 = 160) |
| 577 * 6 channels: 32 ( 32 x 6 = 192) | 582 * 6 channels: 32 ( 32 x 6 = 192) |
| 578 * 7 channels: 32 ( 32 x 7 = 224) | 583 * 7 channels: 32 ( 32 x 7 = 224) |
| 579 * 8 channels: 32 ( 32 x 8 = 256) | 584 * 8 channels: 32 ( 32 x 8 = 256) |
| 580 */ | 585 */ |
| 581 » for (i = 1; i < io->chan_num; i <<= 1) | 586 » for (i = 1; i < fsi->chan_num; i <<= 1) |
| 582 io->fifo_max_num >>= 1; | 587 io->fifo_max_num >>= 1; |
| 583 dev_dbg(dai->dev, "%d channel %d store\n", | 588 dev_dbg(dai->dev, "%d channel %d store\n", |
| 584 » » io->chan_num, io->fifo_max_num); | 589 » » fsi->chan_num, io->fifo_max_num); |
| 585 | 590 |
| 586 » ctrl = is_play ? DOFF_CTL : DIFF_CTL; | 591 » /* |
| 587 | 592 » * set interrupt generation factor |
| 588 » /* set interrupt generation factor */ | 593 » * clear FIFO |
| 589 » fsi_reg_write(fsi, ctrl, IRQ_HALF); | 594 » */ |
| 590 | 595 » if (is_play) { |
| 591 » /* clear FIFO */ | 596 » » fsi_reg_write(fsi,» DOFF_CTL, IRQ_HALF); |
| 592 » fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | 597 » » fsi_reg_mask_set(fsi,» DOFF_CTL, FIFO_CLR, FIFO_CLR); |
| 598 » } else { |
| 599 » » fsi_reg_write(fsi,» DIFF_CTL, IRQ_HALF); |
| 600 » » fsi_reg_mask_set(fsi,» DIFF_CTL, FIFO_CLR, FIFO_CLR); |
| 601 » } |
| 593 } | 602 } |
| 594 | 603 |
| 595 static void fsi_soft_all_reset(struct fsi_master *master) | 604 static void fsi_soft_all_reset(struct fsi_master *master) |
| 596 { | 605 { |
| 597 /* port AB reset */ | 606 /* port AB reset */ |
| 598 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); | 607 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
| 599 mdelay(10); | 608 mdelay(10); |
| 600 | 609 |
| 601 /* soft reset */ | 610 /* soft reset */ |
| 602 fsi_master_mask_set(master, SOFT_RST, FSISR, 0); | 611 fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
| 603 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | 612 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); |
| 604 mdelay(10); | 613 mdelay(10); |
| 605 } | 614 } |
| 606 | 615 |
| 607 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) | 616 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
| 608 { | 617 { |
| 609 struct snd_pcm_runtime *runtime; | 618 struct snd_pcm_runtime *runtime; |
| 610 struct snd_pcm_substream *substream = NULL; | 619 struct snd_pcm_substream *substream = NULL; |
| 611 int is_play = fsi_stream_is_play(stream); | 620 int is_play = fsi_stream_is_play(stream); |
| 612 struct fsi_stream *io = fsi_get_stream(fsi, is_play); | 621 struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
| 613 u32 status_reg = is_play ? DOFF_ST : DIFF_ST; | |
| 614 int data_residue_num; | 622 int data_residue_num; |
| 615 int data_num; | 623 int data_num; |
| 616 int data_num_max; | 624 int data_num_max; |
| 617 int ch_width; | 625 int ch_width; |
| 618 int over_period; | 626 int over_period; |
| 619 void (*fn)(struct fsi_priv *fsi, int size); | 627 void (*fn)(struct fsi_priv *fsi, int size); |
| 620 | 628 |
| 621 if (!fsi || | 629 if (!fsi || |
| 622 !io->substream || | 630 !io->substream || |
| 623 !io->substream->runtime) | 631 !io->substream->runtime) |
| (...skipping 23 matching lines...) Expand all Loading... |
| 647 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, | 655 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, |
| 648 ch_width); | 656 ch_width); |
| 649 | 657 |
| 650 if (is_play) { | 658 if (is_play) { |
| 651 /* | 659 /* |
| 652 * for play-back | 660 * for play-back |
| 653 * | 661 * |
| 654 * data_num_max : number of FSI fifo free space | 662 * data_num_max : number of FSI fifo free space |
| 655 * data_num : number of ALSA residue data | 663 * data_num : number of ALSA residue data |
| 656 */ | 664 */ |
| 657 » » data_num_max = io->fifo_max_num * io->chan_num; | 665 » » data_num_max = io->fifo_max_num * fsi->chan_num; |
| 658 data_num_max -= fsi_get_fifo_data_num(fsi, is_play); | 666 data_num_max -= fsi_get_fifo_data_num(fsi, is_play); |
| 659 | 667 |
| 660 data_num = data_residue_num; | 668 data_num = data_residue_num; |
| 661 | 669 |
| 662 switch (ch_width) { | 670 switch (ch_width) { |
| 663 case 2: | 671 case 2: |
| 664 fn = fsi_dma_soft_push16; | 672 fn = fsi_dma_soft_push16; |
| 665 break; | 673 break; |
| 666 case 4: | 674 case 4: |
| 667 fn = fsi_dma_soft_push32; | 675 fn = fsi_dma_soft_push32; |
| (...skipping 23 matching lines...) Expand all Loading... |
| 691 } | 699 } |
| 692 } | 700 } |
| 693 | 701 |
| 694 data_num = min(data_num, data_num_max); | 702 data_num = min(data_num, data_num_max); |
| 695 | 703 |
| 696 fn(fsi, data_num); | 704 fn(fsi, data_num); |
| 697 | 705 |
| 698 /* update buff_offset */ | 706 /* update buff_offset */ |
| 699 io->buff_offset += fsi_num2offset(data_num, ch_width); | 707 io->buff_offset += fsi_num2offset(data_num, ch_width); |
| 700 | 708 |
| 701 /* check fifo status */ | |
| 702 if (!startup) { | |
| 703 struct snd_soc_dai *dai = fsi_get_dai(substream); | |
| 704 u32 status = fsi_reg_read(fsi, status_reg); | |
| 705 | |
| 706 if (status & ERR_OVER) | |
| 707 dev_err(dai->dev, "over run\n"); | |
| 708 if (status & ERR_UNDER) | |
| 709 dev_err(dai->dev, "under run\n"); | |
| 710 } | |
| 711 fsi_reg_write(fsi, status_reg, 0); | |
| 712 | |
| 713 /* re-enable irq */ | |
| 714 fsi_irq_enable(fsi, is_play); | |
| 715 | |
| 716 if (over_period) | 709 if (over_period) |
| 717 snd_pcm_period_elapsed(substream); | 710 snd_pcm_period_elapsed(substream); |
| 718 | 711 |
| 719 return 0; | 712 return 0; |
| 720 } | 713 } |
| 721 | 714 |
| 722 static int fsi_data_pop(struct fsi_priv *fsi, int startup) | 715 static int fsi_data_pop(struct fsi_priv *fsi) |
| 723 { | 716 { |
| 724 » return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); | 717 » return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
| 725 } | 718 } |
| 726 | 719 |
| 727 static int fsi_data_push(struct fsi_priv *fsi, int startup) | 720 static int fsi_data_push(struct fsi_priv *fsi) |
| 728 { | 721 { |
| 729 » return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); | 722 » return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
| 730 } | 723 } |
| 731 | 724 |
| 732 static irqreturn_t fsi_interrupt(int irq, void *data) | 725 static irqreturn_t fsi_interrupt(int irq, void *data) |
| 733 { | 726 { |
| 734 struct fsi_master *master = data; | 727 struct fsi_master *master = data; |
| 735 u32 int_st = fsi_irq_get_status(master); | 728 u32 int_st = fsi_irq_get_status(master); |
| 736 | 729 |
| 737 /* clear irq status */ | 730 /* clear irq status */ |
| 738 fsi_master_mask_set(master, SOFT_RST, IR, 0); | 731 fsi_master_mask_set(master, SOFT_RST, IR, 0); |
| 739 fsi_master_mask_set(master, SOFT_RST, IR, IR); | 732 fsi_master_mask_set(master, SOFT_RST, IR, IR); |
| 740 | 733 |
| 741 if (int_st & AB_IO(1, AO_SHIFT)) | 734 if (int_st & AB_IO(1, AO_SHIFT)) |
| 742 » » fsi_data_push(&master->fsia, 0); | 735 » » fsi_data_push(&master->fsia); |
| 743 if (int_st & AB_IO(1, BO_SHIFT)) | 736 if (int_st & AB_IO(1, BO_SHIFT)) |
| 744 » » fsi_data_push(&master->fsib, 0); | 737 » » fsi_data_push(&master->fsib); |
| 745 if (int_st & AB_IO(1, AI_SHIFT)) | 738 if (int_st & AB_IO(1, AI_SHIFT)) |
| 746 » » fsi_data_pop(&master->fsia, 0); | 739 » » fsi_data_pop(&master->fsia); |
| 747 if (int_st & AB_IO(1, BI_SHIFT)) | 740 if (int_st & AB_IO(1, BI_SHIFT)) |
| 748 » » fsi_data_pop(&master->fsib, 0); | 741 » » fsi_data_pop(&master->fsib); |
| 749 | 742 |
| 750 » fsi_irq_clear_all_status(master); | 743 » fsi_count_fifo_err(&master->fsia); |
| 744 » fsi_count_fifo_err(&master->fsib); |
| 745 |
| 746 » fsi_irq_clear_status(&master->fsia); |
| 747 » fsi_irq_clear_status(&master->fsib); |
| 751 | 748 |
| 752 return IRQ_HANDLED; | 749 return IRQ_HANDLED; |
| 753 } | 750 } |
| 754 | 751 |
| 755 /* | 752 /* |
| 756 * dai ops | 753 * dai ops |
| 757 */ | 754 */ |
| 758 | 755 |
| 759 static int fsi_dai_startup(struct snd_pcm_substream *substream, | 756 static int fsi_dai_startup(struct snd_pcm_substream *substream, |
| 760 struct snd_soc_dai *dai) | 757 struct snd_soc_dai *dai) |
| 761 { | 758 { |
| 762 struct fsi_priv *fsi = fsi_get_priv(substream); | 759 struct fsi_priv *fsi = fsi_get_priv(substream); |
| 763 struct fsi_master *master = fsi_get_master(fsi); | |
| 764 struct fsi_stream *io; | |
| 765 u32 flags = fsi_get_info_flags(fsi); | 760 u32 flags = fsi_get_info_flags(fsi); |
| 766 u32 fmt; | |
| 767 u32 reg; | |
| 768 u32 data; | 761 u32 data; |
| 769 int is_play = fsi_is_play(substream); | 762 int is_play = fsi_is_play(substream); |
| 770 int is_master; | |
| 771 | |
| 772 io = fsi_get_stream(fsi, is_play); | |
| 773 | 763 |
| 774 pm_runtime_get_sync(dai->dev); | 764 pm_runtime_get_sync(dai->dev); |
| 775 | 765 |
| 776 /* CKG1 */ | |
| 777 data = is_play ? (1 << 0) : (1 << 4); | |
| 778 is_master = fsi_is_master_mode(fsi, is_play); | |
| 779 if (is_master) | |
| 780 fsi_reg_mask_set(fsi, CKG1, data, data); | |
| 781 else | |
| 782 fsi_reg_mask_set(fsi, CKG1, data, 0); | |
| 783 | 766 |
| 784 /* clock inversion (CKG2) */ | 767 /* clock inversion (CKG2) */ |
| 785 data = 0; | 768 data = 0; |
| 786 if (SH_FSI_LRM_INV & flags) | 769 if (SH_FSI_LRM_INV & flags) |
| 787 data |= 1 << 12; | 770 data |= 1 << 12; |
| 788 if (SH_FSI_BRM_INV & flags) | 771 if (SH_FSI_BRM_INV & flags) |
| 789 data |= 1 << 8; | 772 data |= 1 << 8; |
| 790 if (SH_FSI_LRS_INV & flags) | 773 if (SH_FSI_LRS_INV & flags) |
| 791 data |= 1 << 4; | 774 data |= 1 << 4; |
| 792 if (SH_FSI_BRS_INV & flags) | 775 if (SH_FSI_BRS_INV & flags) |
| 793 data |= 1 << 0; | 776 data |= 1 << 0; |
| 794 | 777 |
| 795 fsi_reg_write(fsi, CKG2, data); | 778 fsi_reg_write(fsi, CKG2, data); |
| 796 | 779 |
| 797 /* do fmt, di fmt */ | |
| 798 data = 0; | |
| 799 reg = is_play ? DO_FMT : DI_FMT; | |
| 800 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
| 801 switch (fmt) { | |
| 802 case SH_FSI_FMT_MONO: | |
| 803 data = CR_MONO; | |
| 804 io->chan_num = 1; | |
| 805 break; | |
| 806 case SH_FSI_FMT_MONO_DELAY: | |
| 807 data = CR_MONO_D; | |
| 808 io->chan_num = 1; | |
| 809 break; | |
| 810 case SH_FSI_FMT_PCM: | |
| 811 data = CR_PCM; | |
| 812 io->chan_num = 2; | |
| 813 break; | |
| 814 case SH_FSI_FMT_I2S: | |
| 815 data = CR_I2S; | |
| 816 io->chan_num = 2; | |
| 817 break; | |
| 818 case SH_FSI_FMT_TDM: | |
| 819 io->chan_num = is_play ? | |
| 820 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
| 821 data = CR_TDM | (io->chan_num - 1); | |
| 822 break; | |
| 823 case SH_FSI_FMT_TDM_DELAY: | |
| 824 io->chan_num = is_play ? | |
| 825 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
| 826 data = CR_TDM_D | (io->chan_num - 1); | |
| 827 break; | |
| 828 case SH_FSI_FMT_SPDIF: | |
| 829 if (master->core->ver < 2) { | |
| 830 dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
| 831 return -EINVAL; | |
| 832 } | |
| 833 data = CR_SPDIF; | |
| 834 io->chan_num = 2; | |
| 835 fsi_spdif_clk_ctrl(fsi, 1); | |
| 836 fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); | |
| 837 break; | |
| 838 default: | |
| 839 dev_err(dai->dev, "unknown format.\n"); | |
| 840 return -EINVAL; | |
| 841 } | |
| 842 fsi_reg_write(fsi, reg, data); | |
| 843 | |
| 844 /* irq clear */ | 780 /* irq clear */ |
| 845 fsi_irq_disable(fsi, is_play); | 781 fsi_irq_disable(fsi, is_play); |
| 846 fsi_irq_clear_status(fsi); | 782 fsi_irq_clear_status(fsi); |
| 847 | 783 |
| 848 /* fifo init */ | 784 /* fifo init */ |
| 849 fsi_fifo_init(fsi, is_play, dai); | 785 fsi_fifo_init(fsi, is_play, dai); |
| 850 | 786 |
| 851 return 0; | 787 return 0; |
| 852 } | 788 } |
| 853 | 789 |
| 854 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | 790 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
| 855 struct snd_soc_dai *dai) | 791 struct snd_soc_dai *dai) |
| 856 { | 792 { |
| 857 struct fsi_priv *fsi = fsi_get_priv(substream); | 793 struct fsi_priv *fsi = fsi_get_priv(substream); |
| 858 int is_play = fsi_is_play(substream); | 794 int is_play = fsi_is_play(substream); |
| 859 struct fsi_master *master = fsi_get_master(fsi); | 795 struct fsi_master *master = fsi_get_master(fsi); |
| 860 » int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); | 796 » set_rate_func set_rate; |
| 861 | 797 |
| 862 fsi_irq_disable(fsi, is_play); | 798 fsi_irq_disable(fsi, is_play); |
| 863 fsi_clk_ctrl(fsi, 0); | 799 fsi_clk_ctrl(fsi, 0); |
| 864 | 800 |
| 865 » set_rate = master->info->set_rate; | 801 » set_rate = fsi_get_info_set_rate(master); |
| 866 if (set_rate && fsi->rate) | 802 if (set_rate && fsi->rate) |
| 867 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); | 803 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); |
| 868 fsi->rate = 0; | 804 fsi->rate = 0; |
| 869 | 805 |
| 870 pm_runtime_put_sync(dai->dev); | 806 pm_runtime_put_sync(dai->dev); |
| 871 } | 807 } |
| 872 | 808 |
| 873 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | 809 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
| 874 struct snd_soc_dai *dai) | 810 struct snd_soc_dai *dai) |
| 875 { | 811 { |
| 876 struct fsi_priv *fsi = fsi_get_priv(substream); | 812 struct fsi_priv *fsi = fsi_get_priv(substream); |
| 877 struct snd_pcm_runtime *runtime = substream->runtime; | 813 struct snd_pcm_runtime *runtime = substream->runtime; |
| 878 int is_play = fsi_is_play(substream); | 814 int is_play = fsi_is_play(substream); |
| 879 int ret = 0; | 815 int ret = 0; |
| 880 | 816 |
| 881 switch (cmd) { | 817 switch (cmd) { |
| 882 case SNDRV_PCM_TRIGGER_START: | 818 case SNDRV_PCM_TRIGGER_START: |
| 883 fsi_stream_push(fsi, is_play, substream, | 819 fsi_stream_push(fsi, is_play, substream, |
| 884 frames_to_bytes(runtime, runtime->buffer_size), | 820 frames_to_bytes(runtime, runtime->buffer_size), |
| 885 frames_to_bytes(runtime, runtime->period_size)); | 821 frames_to_bytes(runtime, runtime->period_size)); |
| 886 » » ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); | 822 » » ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
| 823 » » fsi_irq_enable(fsi, is_play); |
| 887 break; | 824 break; |
| 888 case SNDRV_PCM_TRIGGER_STOP: | 825 case SNDRV_PCM_TRIGGER_STOP: |
| 889 fsi_irq_disable(fsi, is_play); | 826 fsi_irq_disable(fsi, is_play); |
| 890 fsi_stream_pop(fsi, is_play); | 827 fsi_stream_pop(fsi, is_play); |
| 891 break; | 828 break; |
| 892 } | 829 } |
| 893 | 830 |
| 894 return ret; | 831 return ret; |
| 895 } | 832 } |
| 896 | 833 |
| 834 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
| 835 { |
| 836 u32 data = 0; |
| 837 |
| 838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 839 case SND_SOC_DAIFMT_I2S: |
| 840 data = CR_I2S; |
| 841 fsi->chan_num = 2; |
| 842 break; |
| 843 case SND_SOC_DAIFMT_LEFT_J: |
| 844 data = CR_PCM; |
| 845 fsi->chan_num = 2; |
| 846 break; |
| 847 default: |
| 848 return -EINVAL; |
| 849 } |
| 850 |
| 851 fsi_reg_write(fsi, DO_FMT, data); |
| 852 fsi_reg_write(fsi, DI_FMT, data); |
| 853 |
| 854 return 0; |
| 855 } |
| 856 |
| 857 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) |
| 858 { |
| 859 struct fsi_master *master = fsi_get_master(fsi); |
| 860 u32 data = 0; |
| 861 |
| 862 if (master->core->ver < 2) |
| 863 return -EINVAL; |
| 864 |
| 865 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; |
| 866 fsi->chan_num = 2; |
| 867 fsi_spdif_clk_ctrl(fsi, 1); |
| 868 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); |
| 869 |
| 870 fsi_reg_write(fsi, DO_FMT, data); |
| 871 fsi_reg_write(fsi, DI_FMT, data); |
| 872 |
| 873 return 0; |
| 874 } |
| 875 |
| 876 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 877 { |
| 878 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); |
| 879 u32 flags = fsi_get_info_flags(fsi); |
| 880 u32 data = 0; |
| 881 int ret; |
| 882 |
| 883 pm_runtime_get_sync(dai->dev); |
| 884 |
| 885 /* set master/slave audio interface */ |
| 886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 887 case SND_SOC_DAIFMT_CBM_CFM: |
| 888 data = DIMD | DOMD; |
| 889 break; |
| 890 case SND_SOC_DAIFMT_CBS_CFS: |
| 891 break; |
| 892 default: |
| 893 ret = -EINVAL; |
| 894 goto set_fmt_exit; |
| 895 } |
| 896 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); |
| 897 |
| 898 /* set format */ |
| 899 switch (flags & SH_FSI_FMT_MASK) { |
| 900 case SH_FSI_FMT_DAI: |
| 901 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); |
| 902 break; |
| 903 case SH_FSI_FMT_SPDIF: |
| 904 ret = fsi_set_fmt_spdif(fsi); |
| 905 break; |
| 906 default: |
| 907 ret = -EINVAL; |
| 908 } |
| 909 |
| 910 set_fmt_exit: |
| 911 pm_runtime_put_sync(dai->dev); |
| 912 |
| 913 return ret; |
| 914 } |
| 915 |
| 897 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, | 916 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
| 898 struct snd_pcm_hw_params *params, | 917 struct snd_pcm_hw_params *params, |
| 899 struct snd_soc_dai *dai) | 918 struct snd_soc_dai *dai) |
| 900 { | 919 { |
| 901 struct fsi_priv *fsi = fsi_get_priv(substream); | 920 struct fsi_priv *fsi = fsi_get_priv(substream); |
| 902 struct fsi_master *master = fsi_get_master(fsi); | 921 struct fsi_master *master = fsi_get_master(fsi); |
| 903 » int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); | 922 » set_rate_func set_rate; |
| 904 int fsi_ver = master->core->ver; | 923 int fsi_ver = master->core->ver; |
| 905 long rate = params_rate(params); | 924 long rate = params_rate(params); |
| 906 int ret; | 925 int ret; |
| 907 | 926 |
| 908 » set_rate = master->info->set_rate; | 927 » set_rate = fsi_get_info_set_rate(master); |
| 909 if (!set_rate) | 928 if (!set_rate) |
| 910 return 0; | 929 return 0; |
| 911 | 930 |
| 912 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); | 931 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); |
| 913 if (ret < 0) /* error */ | 932 if (ret < 0) /* error */ |
| 914 return ret; | 933 return ret; |
| 915 | 934 |
| 916 fsi->rate = rate; | 935 fsi->rate = rate; |
| 917 if (ret > 0) { | 936 if (ret > 0) { |
| 918 u32 data = 0; | 937 u32 data = 0; |
| (...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 973 } | 992 } |
| 974 | 993 |
| 975 return ret; | 994 return ret; |
| 976 | 995 |
| 977 } | 996 } |
| 978 | 997 |
| 979 static struct snd_soc_dai_ops fsi_dai_ops = { | 998 static struct snd_soc_dai_ops fsi_dai_ops = { |
| 980 .startup = fsi_dai_startup, | 999 .startup = fsi_dai_startup, |
| 981 .shutdown = fsi_dai_shutdown, | 1000 .shutdown = fsi_dai_shutdown, |
| 982 .trigger = fsi_dai_trigger, | 1001 .trigger = fsi_dai_trigger, |
| 1002 .set_fmt = fsi_dai_set_fmt, |
| 983 .hw_params = fsi_dai_hw_params, | 1003 .hw_params = fsi_dai_hw_params, |
| 984 }; | 1004 }; |
| 985 | 1005 |
| 986 /* | 1006 /* |
| 987 * pcm ops | 1007 * pcm ops |
| 988 */ | 1008 */ |
| 989 | 1009 |
| 990 static struct snd_pcm_hardware fsi_pcm_hardware = { | 1010 static struct snd_pcm_hardware fsi_pcm_hardware = { |
| 991 .info = SNDRV_PCM_INFO_INTERLEAVED | | 1011 .info = SNDRV_PCM_INFO_INTERLEAVED | |
| 992 SNDRV_PCM_INFO_MMAP | | 1012 SNDRV_PCM_INFO_MMAP | |
| (...skipping 174 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1167 | 1187 |
| 1168 /* master setting */ | 1188 /* master setting */ |
| 1169 master->irq = irq; | 1189 master->irq = irq; |
| 1170 master->info = pdev->dev.platform_data; | 1190 master->info = pdev->dev.platform_data; |
| 1171 master->core = (struct fsi_core *)id_entry->driver_data; | 1191 master->core = (struct fsi_core *)id_entry->driver_data; |
| 1172 spin_lock_init(&master->lock); | 1192 spin_lock_init(&master->lock); |
| 1173 | 1193 |
| 1174 /* FSI A setting */ | 1194 /* FSI A setting */ |
| 1175 master->fsia.base = master->base; | 1195 master->fsia.base = master->base; |
| 1176 master->fsia.master = master; | 1196 master->fsia.master = master; |
| 1177 master->fsia.mst_ctrl = A_MST_CTLR; | |
| 1178 | 1197 |
| 1179 /* FSI B setting */ | 1198 /* FSI B setting */ |
| 1180 master->fsib.base = master->base + 0x40; | 1199 master->fsib.base = master->base + 0x40; |
| 1181 master->fsib.master = master; | 1200 master->fsib.master = master; |
| 1182 master->fsib.mst_ctrl = B_MST_CTLR; | |
| 1183 | 1201 |
| 1184 pm_runtime_enable(&pdev->dev); | 1202 pm_runtime_enable(&pdev->dev); |
| 1185 pm_runtime_resume(&pdev->dev); | 1203 pm_runtime_resume(&pdev->dev); |
| 1186 dev_set_drvdata(&pdev->dev, master); | 1204 dev_set_drvdata(&pdev->dev, master); |
| 1187 | 1205 |
| 1188 fsi_soft_all_reset(master); | 1206 fsi_soft_all_reset(master); |
| 1189 | 1207 |
| 1190 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, | 1208 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
| 1191 id_entry->name, master); | 1209 id_entry->name, master); |
| 1192 if (ret) { | 1210 if (ret) { |
| (...skipping 66 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1259 .imsk = IMSK, | 1277 .imsk = IMSK, |
| 1260 }; | 1278 }; |
| 1261 | 1279 |
| 1262 static struct fsi_core fsi2_core = { | 1280 static struct fsi_core fsi2_core = { |
| 1263 .ver = 2, | 1281 .ver = 2, |
| 1264 | 1282 |
| 1265 /* Interrupt */ | 1283 /* Interrupt */ |
| 1266 .int_st = CPU_INT_ST, | 1284 .int_st = CPU_INT_ST, |
| 1267 .iemsk = CPU_IEMSK, | 1285 .iemsk = CPU_IEMSK, |
| 1268 .imsk = CPU_IMSK, | 1286 .imsk = CPU_IMSK, |
| 1287 .a_mclk = A_MST_CTLR, |
| 1288 .b_mclk = B_MST_CTLR, |
| 1269 }; | 1289 }; |
| 1270 | 1290 |
| 1271 static struct platform_device_id fsi_id_table[] = { | 1291 static struct platform_device_id fsi_id_table[] = { |
| 1272 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, | 1292 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
| 1273 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | 1293 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, |
| 1274 {}, | 1294 {}, |
| 1275 }; | 1295 }; |
| 1276 MODULE_DEVICE_TABLE(platform, fsi_id_table); | 1296 MODULE_DEVICE_TABLE(platform, fsi_id_table); |
| 1277 | 1297 |
| 1278 static struct platform_driver fsi_driver = { | 1298 static struct platform_driver fsi_driver = { |
| (...skipping 15 matching lines...) Expand all Loading... |
| 1294 { | 1314 { |
| 1295 platform_driver_unregister(&fsi_driver); | 1315 platform_driver_unregister(&fsi_driver); |
| 1296 } | 1316 } |
| 1297 | 1317 |
| 1298 module_init(fsi_mobile_init); | 1318 module_init(fsi_mobile_init); |
| 1299 module_exit(fsi_mobile_exit); | 1319 module_exit(fsi_mobile_exit); |
| 1300 | 1320 |
| 1301 MODULE_LICENSE("GPL"); | 1321 MODULE_LICENSE("GPL"); |
| 1302 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | 1322 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); |
| 1303 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | 1323 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |
| OLD | NEW |