CHROMIUM: ASoC: Import entire upstream ASoC tree

sound/soc/omap/omap-mcbsp.c

 /*
  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
  *
  * Copyright (C) 2008 Nokia Corporation
  *
  * Contact: Jarkko Nikula <jhnikula@gmail.com>
  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ skipping 84 matching lines @@
 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
 #endif
 };
 #else
 static const int omap24xx_dma_reqs[][2] = {};
 #endif
 
+#if defined(CONFIG_ARCH_OMAP4)
+static const int omap44xx_dma_reqs[][2] = {
+        { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
+        { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
+        { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
+        { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
+};
+#else
+static const int omap44xx_dma_reqs[][2] = {};
+#endif
+
 #if defined(CONFIG_ARCH_OMAP2420)
 static const unsigned long omap2420_mcbsp_port[][2] = {
         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 };
 #else
 static const unsigned long omap2420_mcbsp_port[][2] = {};
 #endif
@@ skipping 25 matching lines @@
           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 };
 #else
 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 #endif
 
+#if defined(CONFIG_ARCH_OMAP4)
+static const unsigned long omap44xx_mcbsp_port[][2] = {
+        { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+          OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+        { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+          OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+        { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+          OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+        { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+          OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+};
+#else
+static const unsigned long omap44xx_mcbsp_port[][2] = {};
+#endif
+
 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
         struct omap_pcm_dma_data *dma_data;
         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
         int words;
 
         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
@@ skipping 57 matching lines @@
          * For example on McBSP3:
          * 16bit samples: size is 128 * 2 = 256 bytes
          * 32bit samples: size is 128 * 4 = 512 bytes
          * It is simpler to place constraint for buffer and period based on
          * channels.
          * McBSP3 as example again (16 or 32 bit samples):
          * 1 channel (mono): size is 128 frames (128 words)
          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
          */
-        if (cpu_is_omap343x()) {
+        if (cpu_is_omap343x() || cpu_is_omap44xx()) {
                 /*
                 * Rule for the buffer size. We should not allow
                 * smaller buffer than the FIFO size to avoid underruns
                 */
                 snd_pcm_hw_rule_add(substream->runtime, 0,
                                     SNDRV_PCM_HW_PARAM_CHANNELS,
                                     omap_mcbsp_hwrule_min_buffersize,
                                     mcbsp_data,
                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 
@@ skipping 87 matching lines @@
                 port = omap1_mcbsp_port[bus_id][substream->stream];
         } else if (cpu_is_omap2420()) {
                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
                 port = omap2420_mcbsp_port[bus_id][substream->stream];
         } else if (cpu_is_omap2430()) {
                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
                 port = omap2430_mcbsp_port[bus_id][substream->stream];
         } else if (cpu_is_omap343x()) {
                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
+         } else if (cpu_is_omap44xx()) {
+                dma = omap44xx_dma_reqs[bus_id][substream->stream];
+                port = omap44xx_mcbsp_port[bus_id][substream->stream];
         } else {
                 return -ENODEV;
         }
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S16_LE:
                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
                 wlen = 16;
                 break;
         case SNDRV_PCM_FORMAT_S32_LE:
                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
@@ skipping 146 matching lines @@
 
         if (mcbsp_data->configured)
                 return 0;
 
         mcbsp_data->fmt = fmt;
         memset(regs, 0, sizeof(*regs));
         /* Generic McBSP register settings */
         regs->spcr2     |= XINTM(3) | FREE;
         regs->spcr1     |= RINTM(3);
         /* RFIG and XFIG are not defined in 34xx */
-        if (!cpu_is_omap34xx()) {
+        if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
                 regs->rcr2      |= RFIG;
                 regs->xcr2      |= XFIG;
         }
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
         }
 
         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
         case SND_SOC_DAIFMT_I2S:
                 /* 1-bit data delay */
                 regs->rcr2      |= RDATDLY(1);
                 regs->xcr2      |= XDATDLY(1);
                 break;
@@ skipping 349 matching lines @@
 
 static void __exit snd_omap_mcbsp_exit(void)
 {
         platform_driver_unregister(&asoc_mcbsp_driver);
 }
 module_exit(snd_omap_mcbsp_exit);
 
 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 MODULE_LICENSE("GPL");