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| 1 /* |
| 2 * wm8995.c -- WM8995 ALSA SoC Audio driver |
| 3 * |
| 4 * Copyright 2010 Wolfson Microelectronics plc |
| 5 * |
| 6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> |
| 7 * |
| 8 * Based on wm8994.c and wm_hubs.c by Mark Brown |
| 9 * |
| 10 * This program is free software; you can redistribute it and/or modify |
| 11 * it under the terms of the GNU General Public License version 2 as |
| 12 * published by the Free Software Foundation. |
| 13 */ |
| 14 |
| 15 #include <linux/module.h> |
| 16 #include <linux/moduleparam.h> |
| 17 #include <linux/init.h> |
| 18 #include <linux/delay.h> |
| 19 #include <linux/pm.h> |
| 20 #include <linux/i2c.h> |
| 21 #include <linux/spi/spi.h> |
| 22 #include <linux/regulator/consumer.h> |
| 23 #include <linux/slab.h> |
| 24 #include <sound/core.h> |
| 25 #include <sound/pcm.h> |
| 26 #include <sound/pcm_params.h> |
| 27 #include <sound/soc.h> |
| 28 #include <sound/soc-dapm.h> |
| 29 #include <sound/initval.h> |
| 30 #include <sound/tlv.h> |
| 31 |
| 32 #include "wm8995.h" |
| 33 |
| 34 #define WM8995_NUM_SUPPLIES 8 |
| 35 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { |
| 36 "DCVDD", |
| 37 "DBVDD1", |
| 38 "DBVDD2", |
| 39 "DBVDD3", |
| 40 "AVDD1", |
| 41 "AVDD2", |
| 42 "CPVDD", |
| 43 "MICVDD" |
| 44 }; |
| 45 |
| 46 static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = { |
| 47 [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, |
| 48 [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, |
| 49 [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, |
| 50 [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25, |
| 51 [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060, |
| 52 [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083, |
| 53 [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050, |
| 54 [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040, |
| 55 [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000, |
| 56 [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0, |
| 57 [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0, |
| 58 [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200, |
| 59 [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098, |
| 60 [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318, |
| 61 [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8, |
| 62 [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5, |
| 63 [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558, |
| 64 [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103, |
| 65 [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318, |
| 66 [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8, |
| 67 [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5, |
| 68 [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558, |
| 69 [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103, |
| 70 [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0, |
| 71 [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200, |
| 72 [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318, |
| 73 [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8, |
| 74 [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5, |
| 75 [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558, |
| 76 [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103, |
| 77 [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002, |
| 78 [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101, |
| 79 [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101, |
| 80 [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101, |
| 81 [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff, |
| 82 [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002, |
| 83 [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001, |
| 84 [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f, |
| 85 [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104, |
| 86 [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050, |
| 87 [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003, |
| 88 [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b, |
| 89 [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff, |
| 90 [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff, |
| 91 [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001, |
| 92 [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001, |
| 93 [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003, |
| 94 [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401, |
| 95 [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060, |
| 96 [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff, |
| 97 [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff, |
| 98 [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff, |
| 99 [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006, |
| 100 [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006, |
| 101 [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061, |
| 102 [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003, |
| 103 [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106, |
| 104 [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502, |
| 105 [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff, |
| 106 [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff, |
| 107 [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001, |
| 108 [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f, |
| 109 [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106, |
| 110 [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050, |
| 111 [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b, |
| 112 [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff, |
| 113 [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff, |
| 114 [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff, |
| 115 [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100, |
| 116 [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff, |
| 117 [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff, |
| 118 [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff, |
| 119 [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff, |
| 120 [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102, |
| 121 [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff, |
| 122 [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff, |
| 123 [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff, |
| 124 [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff, |
| 125 [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601, |
| 126 [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304, |
| 127 [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100 |
| 128 }; |
| 129 |
| 130 struct fll_config { |
| 131 int src; |
| 132 int in; |
| 133 int out; |
| 134 }; |
| 135 |
| 136 struct wm8995_priv { |
| 137 enum snd_soc_control_type control_type; |
| 138 int sysclk[2]; |
| 139 int mclk[2]; |
| 140 int aifclk[2]; |
| 141 struct fll_config fll[2], fll_suspend[2]; |
| 142 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; |
| 143 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; |
| 144 struct snd_soc_codec *codec; |
| 145 }; |
| 146 |
| 147 /* |
| 148 * We can't use the same notifier block for more than one supply and |
| 149 * there's no way I can see to get from a callback to the caller |
| 150 * except container_of(). |
| 151 */ |
| 152 #define WM8995_REGULATOR_EVENT(n) \ |
| 153 static int wm8995_regulator_event_##n(struct notifier_block *nb, \ |
| 154 unsigned long event, void *data) \ |
| 155 { \ |
| 156 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ |
| 157 disable_nb[n]); \ |
| 158 if (event & REGULATOR_EVENT_DISABLE) { \ |
| 159 wm8995->codec->cache_sync = 1; \ |
| 160 } \ |
| 161 return 0; \ |
| 162 } |
| 163 |
| 164 WM8995_REGULATOR_EVENT(0) |
| 165 WM8995_REGULATOR_EVENT(1) |
| 166 WM8995_REGULATOR_EVENT(2) |
| 167 WM8995_REGULATOR_EVENT(3) |
| 168 WM8995_REGULATOR_EVENT(4) |
| 169 WM8995_REGULATOR_EVENT(5) |
| 170 WM8995_REGULATOR_EVENT(6) |
| 171 WM8995_REGULATOR_EVENT(7) |
| 172 |
| 173 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); |
| 174 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); |
| 175 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); |
| 176 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); |
| 177 |
| 178 static const char *in1l_text[] = { |
| 179 "Differential", "Single-ended IN1LN", "Single-ended IN1LP" |
| 180 }; |
| 181 |
| 182 static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, |
| 183 2, in1l_text); |
| 184 |
| 185 static const char *in1r_text[] = { |
| 186 "Differential", "Single-ended IN1RN", "Single-ended IN1RP" |
| 187 }; |
| 188 |
| 189 static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, |
| 190 0, in1r_text); |
| 191 |
| 192 static const char *dmic_src_text[] = { |
| 193 "DMICDAT1", "DMICDAT2", "DMICDAT3" |
| 194 }; |
| 195 |
| 196 static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, |
| 197 8, dmic_src_text); |
| 198 static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, |
| 199 6, dmic_src_text); |
| 200 |
| 201 static const struct snd_kcontrol_new wm8995_snd_controls[] = { |
| 202 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, |
| 203 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 204 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, |
| 205 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), |
| 206 |
| 207 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, |
| 208 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 209 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, |
| 210 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), |
| 211 |
| 212 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, |
| 213 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 214 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, |
| 215 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 216 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, |
| 217 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 218 |
| 219 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, |
| 220 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), |
| 221 |
| 222 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, |
| 223 4, 3, 0, in1l_boost_tlv), |
| 224 |
| 225 SOC_ENUM("IN1L Mode", in1l_enum), |
| 226 SOC_ENUM("IN1R Mode", in1r_enum), |
| 227 |
| 228 SOC_ENUM("DMIC1 SRC", dmic_src1_enum), |
| 229 SOC_ENUM("DMIC2 SRC", dmic_src2_enum), |
| 230 |
| 231 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, |
| 232 24, 0, sidetone_tlv), |
| 233 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, |
| 234 24, 0, sidetone_tlv), |
| 235 |
| 236 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, |
| 237 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 238 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, |
| 239 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), |
| 240 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, |
| 241 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) |
| 242 }; |
| 243 |
| 244 static void wm8995_update_class_w(struct snd_soc_codec *codec) |
| 245 { |
| 246 int enable = 1; |
| 247 int source = 0; /* GCC flow analysis can't track enable */ |
| 248 int reg, reg_r; |
| 249 |
| 250 /* We also need the same setting for L/R and only one path */ |
| 251 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); |
| 252 switch (reg) { |
| 253 case WM8995_AIF2DACL_TO_DAC1L: |
| 254 dev_dbg(codec->dev, "Class W source AIF2DAC\n"); |
| 255 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
| 256 break; |
| 257 case WM8995_AIF1DAC2L_TO_DAC1L: |
| 258 dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); |
| 259 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
| 260 break; |
| 261 case WM8995_AIF1DAC1L_TO_DAC1L: |
| 262 dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); |
| 263 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
| 264 break; |
| 265 default: |
| 266 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); |
| 267 enable = 0; |
| 268 break; |
| 269 } |
| 270 |
| 271 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); |
| 272 if (reg_r != reg) { |
| 273 dev_dbg(codec->dev, "Left and right DAC mixers different\n"); |
| 274 enable = 0; |
| 275 } |
| 276 |
| 277 if (enable) { |
| 278 dev_dbg(codec->dev, "Class W enabled\n"); |
| 279 snd_soc_update_bits(codec, WM8995_CLASS_W_1, |
| 280 WM8995_CP_DYN_PWR_MASK | |
| 281 WM8995_CP_DYN_SRC_SEL_MASK, |
| 282 source | WM8995_CP_DYN_PWR); |
| 283 } else { |
| 284 dev_dbg(codec->dev, "Class W disabled\n"); |
| 285 snd_soc_update_bits(codec, WM8995_CLASS_W_1, |
| 286 WM8995_CP_DYN_PWR_MASK, 0); |
| 287 } |
| 288 } |
| 289 |
| 290 static int check_clk_sys(struct snd_soc_dapm_widget *source, |
| 291 struct snd_soc_dapm_widget *sink) |
| 292 { |
| 293 unsigned int reg; |
| 294 const char *clk; |
| 295 |
| 296 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); |
| 297 /* Check what we're currently using for CLK_SYS */ |
| 298 if (reg & WM8995_SYSCLK_SRC) |
| 299 clk = "AIF2CLK"; |
| 300 else |
| 301 clk = "AIF1CLK"; |
| 302 return !strcmp(source->name, clk); |
| 303 } |
| 304 |
| 305 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, |
| 306 struct snd_ctl_elem_value *ucontrol) |
| 307 { |
| 308 struct snd_soc_dapm_widget *w; |
| 309 struct snd_soc_codec *codec; |
| 310 int ret; |
| 311 |
| 312 w = snd_kcontrol_chip(kcontrol); |
| 313 codec = w->codec; |
| 314 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); |
| 315 wm8995_update_class_w(codec); |
| 316 return ret; |
| 317 } |
| 318 |
| 319 static int hp_supply_event(struct snd_soc_dapm_widget *w, |
| 320 struct snd_kcontrol *kcontrol, int event) |
| 321 { |
| 322 struct snd_soc_codec *codec; |
| 323 struct wm8995_priv *wm8995; |
| 324 |
| 325 codec = w->codec; |
| 326 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 327 |
| 328 switch (event) { |
| 329 case SND_SOC_DAPM_PRE_PMU: |
| 330 /* Enable the headphone amp */ |
| 331 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, |
| 332 WM8995_HPOUT1L_ENA_MASK | |
| 333 WM8995_HPOUT1R_ENA_MASK, |
| 334 WM8995_HPOUT1L_ENA | |
| 335 WM8995_HPOUT1R_ENA); |
| 336 |
| 337 /* Enable the second stage */ |
| 338 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, |
| 339 WM8995_HPOUT1L_DLY_MASK | |
| 340 WM8995_HPOUT1R_DLY_MASK, |
| 341 WM8995_HPOUT1L_DLY | |
| 342 WM8995_HPOUT1R_DLY); |
| 343 break; |
| 344 case SND_SOC_DAPM_PRE_PMD: |
| 345 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, |
| 346 WM8995_CP_ENA_MASK, 0); |
| 347 break; |
| 348 } |
| 349 |
| 350 return 0; |
| 351 } |
| 352 |
| 353 static void dc_servo_cmd(struct snd_soc_codec *codec, |
| 354 unsigned int reg, unsigned int val, unsigned int mask) |
| 355 { |
| 356 int timeout = 10; |
| 357 |
| 358 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", |
| 359 __func__, reg, val, mask); |
| 360 |
| 361 snd_soc_write(codec, reg, val); |
| 362 while (timeout--) { |
| 363 msleep(10); |
| 364 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); |
| 365 if ((val & mask) == mask) |
| 366 return; |
| 367 } |
| 368 |
| 369 dev_err(codec->dev, "Timed out waiting for DC Servo\n"); |
| 370 } |
| 371 |
| 372 static int hp_event(struct snd_soc_dapm_widget *w, |
| 373 struct snd_kcontrol *kcontrol, int event) |
| 374 { |
| 375 struct snd_soc_codec *codec; |
| 376 unsigned int reg; |
| 377 |
| 378 codec = w->codec; |
| 379 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); |
| 380 |
| 381 switch (event) { |
| 382 case SND_SOC_DAPM_POST_PMU: |
| 383 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, |
| 384 WM8995_CP_ENA_MASK, WM8995_CP_ENA); |
| 385 |
| 386 msleep(5); |
| 387 |
| 388 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, |
| 389 WM8995_HPOUT1L_ENA_MASK | |
| 390 WM8995_HPOUT1R_ENA_MASK, |
| 391 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); |
| 392 |
| 393 udelay(20); |
| 394 |
| 395 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; |
| 396 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); |
| 397 |
| 398 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | |
| 399 WM8995_DCS_ENA_CHAN_1); |
| 400 |
| 401 dc_servo_cmd(codec, WM8995_DC_SERVO_2, |
| 402 WM8995_DCS_TRIG_STARTUP_0 | |
| 403 WM8995_DCS_TRIG_STARTUP_1, |
| 404 WM8995_DCS_TRIG_DAC_WR_0 | |
| 405 WM8995_DCS_TRIG_DAC_WR_1); |
| 406 |
| 407 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | |
| 408 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; |
| 409 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); |
| 410 |
| 411 break; |
| 412 case SND_SOC_DAPM_PRE_PMD: |
| 413 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, |
| 414 WM8995_HPOUT1L_OUTP_MASK | |
| 415 WM8995_HPOUT1R_OUTP_MASK | |
| 416 WM8995_HPOUT1L_RMV_SHORT_MASK | |
| 417 WM8995_HPOUT1R_RMV_SHORT_MASK, 0); |
| 418 |
| 419 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, |
| 420 WM8995_HPOUT1L_DLY_MASK | |
| 421 WM8995_HPOUT1R_DLY_MASK, 0); |
| 422 |
| 423 snd_soc_write(codec, WM8995_DC_SERVO_1, 0); |
| 424 |
| 425 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, |
| 426 WM8995_HPOUT1L_ENA_MASK | |
| 427 WM8995_HPOUT1R_ENA_MASK, |
| 428 0); |
| 429 break; |
| 430 } |
| 431 |
| 432 return 0; |
| 433 } |
| 434 |
| 435 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) |
| 436 { |
| 437 struct wm8995_priv *wm8995; |
| 438 int rate; |
| 439 int reg1 = 0; |
| 440 int offset; |
| 441 |
| 442 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 443 |
| 444 if (aif) |
| 445 offset = 4; |
| 446 else |
| 447 offset = 0; |
| 448 |
| 449 switch (wm8995->sysclk[aif]) { |
| 450 case WM8995_SYSCLK_MCLK1: |
| 451 rate = wm8995->mclk[0]; |
| 452 break; |
| 453 case WM8995_SYSCLK_MCLK2: |
| 454 reg1 |= 0x8; |
| 455 rate = wm8995->mclk[1]; |
| 456 break; |
| 457 case WM8995_SYSCLK_FLL1: |
| 458 reg1 |= 0x10; |
| 459 rate = wm8995->fll[0].out; |
| 460 break; |
| 461 case WM8995_SYSCLK_FLL2: |
| 462 reg1 |= 0x18; |
| 463 rate = wm8995->fll[1].out; |
| 464 break; |
| 465 default: |
| 466 return -EINVAL; |
| 467 } |
| 468 |
| 469 if (rate >= 13500000) { |
| 470 rate /= 2; |
| 471 reg1 |= WM8995_AIF1CLK_DIV; |
| 472 |
| 473 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", |
| 474 aif + 1, rate); |
| 475 } |
| 476 |
| 477 wm8995->aifclk[aif] = rate; |
| 478 |
| 479 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, |
| 480 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, |
| 481 reg1); |
| 482 return 0; |
| 483 } |
| 484 |
| 485 static int configure_clock(struct snd_soc_codec *codec) |
| 486 { |
| 487 struct wm8995_priv *wm8995; |
| 488 int old, new; |
| 489 |
| 490 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 491 |
| 492 /* Bring up the AIF clocks first */ |
| 493 configure_aif_clock(codec, 0); |
| 494 configure_aif_clock(codec, 1); |
| 495 |
| 496 /* |
| 497 * Then switch CLK_SYS over to the higher of them; a change |
| 498 * can only happen as a result of a clocking change which can |
| 499 * only be made outside of DAPM so we can safely redo the |
| 500 * clocking. |
| 501 */ |
| 502 |
| 503 /* If they're equal it doesn't matter which is used */ |
| 504 if (wm8995->aifclk[0] == wm8995->aifclk[1]) |
| 505 return 0; |
| 506 |
| 507 if (wm8995->aifclk[0] < wm8995->aifclk[1]) |
| 508 new = WM8995_SYSCLK_SRC; |
| 509 else |
| 510 new = 0; |
| 511 |
| 512 old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC; |
| 513 |
| 514 /* If there's no change then we're done. */ |
| 515 if (old == new) |
| 516 return 0; |
| 517 |
| 518 snd_soc_update_bits(codec, WM8995_CLOCKING_1, |
| 519 WM8995_SYSCLK_SRC_MASK, new); |
| 520 |
| 521 snd_soc_dapm_sync(&codec->dapm); |
| 522 |
| 523 return 0; |
| 524 } |
| 525 |
| 526 static int clk_sys_event(struct snd_soc_dapm_widget *w, |
| 527 struct snd_kcontrol *kcontrol, int event) |
| 528 { |
| 529 struct snd_soc_codec *codec; |
| 530 |
| 531 codec = w->codec; |
| 532 |
| 533 switch (event) { |
| 534 case SND_SOC_DAPM_PRE_PMU: |
| 535 return configure_clock(codec); |
| 536 |
| 537 case SND_SOC_DAPM_POST_PMD: |
| 538 configure_clock(codec); |
| 539 break; |
| 540 } |
| 541 |
| 542 return 0; |
| 543 } |
| 544 |
| 545 static const char *sidetone_text[] = { |
| 546 "ADC/DMIC1", "DMIC2", |
| 547 }; |
| 548 |
| 549 static const struct soc_enum sidetone1_enum = |
| 550 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); |
| 551 |
| 552 static const struct snd_kcontrol_new sidetone1_mux = |
| 553 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); |
| 554 |
| 555 static const struct soc_enum sidetone2_enum = |
| 556 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); |
| 557 |
| 558 static const struct snd_kcontrol_new sidetone2_mux = |
| 559 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); |
| 560 |
| 561 static const struct snd_kcontrol_new aif1adc1l_mix[] = { |
| 562 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, |
| 563 1, 1, 0), |
| 564 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, |
| 565 0, 1, 0), |
| 566 }; |
| 567 |
| 568 static const struct snd_kcontrol_new aif1adc1r_mix[] = { |
| 569 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, |
| 570 1, 1, 0), |
| 571 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, |
| 572 0, 1, 0), |
| 573 }; |
| 574 |
| 575 static const struct snd_kcontrol_new aif1adc2l_mix[] = { |
| 576 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, |
| 577 1, 1, 0), |
| 578 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, |
| 579 0, 1, 0), |
| 580 }; |
| 581 |
| 582 static const struct snd_kcontrol_new aif1adc2r_mix[] = { |
| 583 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, |
| 584 1, 1, 0), |
| 585 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, |
| 586 0, 1, 0), |
| 587 }; |
| 588 |
| 589 static const struct snd_kcontrol_new dac1l_mix[] = { |
| 590 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_RO
UTING, |
| 591 5, 1, 0), |
| 592 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROU
TING, |
| 593 4, 1, 0), |
| 594 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, |
| 595 2, 1, 0), |
| 596 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, |
| 597 1, 1, 0), |
| 598 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, |
| 599 0, 1, 0), |
| 600 }; |
| 601 |
| 602 static const struct snd_kcontrol_new dac1r_mix[] = { |
| 603 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_R
OUTING, |
| 604 5, 1, 0), |
| 605 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_RO
UTING, |
| 606 4, 1, 0), |
| 607 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, |
| 608 2, 1, 0), |
| 609 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, |
| 610 1, 1, 0), |
| 611 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, |
| 612 0, 1, 0), |
| 613 }; |
| 614 |
| 615 static const struct snd_kcontrol_new aif2dac2l_mix[] = { |
| 616 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, |
| 617 5, 1, 0), |
| 618 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, |
| 619 4, 1, 0), |
| 620 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, |
| 621 2, 1, 0), |
| 622 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, |
| 623 1, 1, 0), |
| 624 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, |
| 625 0, 1, 0), |
| 626 }; |
| 627 |
| 628 static const struct snd_kcontrol_new aif2dac2r_mix[] = { |
| 629 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING
, |
| 630 5, 1, 0), |
| 631 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, |
| 632 4, 1, 0), |
| 633 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, |
| 634 2, 1, 0), |
| 635 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, |
| 636 1, 1, 0), |
| 637 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, |
| 638 0, 1, 0), |
| 639 }; |
| 640 |
| 641 static const struct snd_kcontrol_new in1l_pga = |
| 642 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); |
| 643 |
| 644 static const struct snd_kcontrol_new in1r_pga = |
| 645 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); |
| 646 |
| 647 static const char *adc_mux_text[] = { |
| 648 "ADC", |
| 649 "DMIC", |
| 650 }; |
| 651 |
| 652 static const struct soc_enum adc_enum = |
| 653 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); |
| 654 |
| 655 static const struct snd_kcontrol_new adcl_mux = |
| 656 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); |
| 657 |
| 658 static const struct snd_kcontrol_new adcr_mux = |
| 659 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); |
| 660 |
| 661 static const char *spk_src_text[] = { |
| 662 "DAC1L", "DAC1R", "DAC2L", "DAC2R" |
| 663 }; |
| 664 |
| 665 static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, |
| 666 0, spk_src_text); |
| 667 static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, |
| 668 0, spk_src_text); |
| 669 static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, |
| 670 0, spk_src_text); |
| 671 static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, |
| 672 0, spk_src_text); |
| 673 |
| 674 static const struct snd_kcontrol_new spk1l_mux = |
| 675 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); |
| 676 static const struct snd_kcontrol_new spk1r_mux = |
| 677 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); |
| 678 static const struct snd_kcontrol_new spk2l_mux = |
| 679 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); |
| 680 static const struct snd_kcontrol_new spk2r_mux = |
| 681 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); |
| 682 |
| 683 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { |
| 684 SND_SOC_DAPM_INPUT("DMIC1DAT"), |
| 685 SND_SOC_DAPM_INPUT("DMIC2DAT"), |
| 686 |
| 687 SND_SOC_DAPM_INPUT("IN1L"), |
| 688 SND_SOC_DAPM_INPUT("IN1R"), |
| 689 |
| 690 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, |
| 691 &in1l_pga, 1), |
| 692 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, |
| 693 &in1r_pga, 1), |
| 694 |
| 695 SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0), |
| 696 SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0), |
| 697 |
| 698 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), |
| 699 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), |
| 700 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), |
| 701 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), |
| 702 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), |
| 703 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, |
| 704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 705 |
| 706 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, |
| 707 WM8995_POWER_MANAGEMENT_3, 9, 0), |
| 708 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, |
| 709 WM8995_POWER_MANAGEMENT_3, 8, 0), |
| 710 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, |
| 711 SND_SOC_NOPM, 0, 0), |
| 712 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", |
| 713 0, WM8995_POWER_MANAGEMENT_3, 11, 0), |
| 714 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", |
| 715 0, WM8995_POWER_MANAGEMENT_3, 10, 0), |
| 716 |
| 717 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, |
| 718 &adcl_mux), |
| 719 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, |
| 720 &adcr_mux), |
| 721 |
| 722 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), |
| 723 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), |
| 724 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), |
| 725 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), |
| 726 |
| 727 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), |
| 728 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), |
| 729 |
| 730 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, |
| 731 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), |
| 732 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, |
| 733 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), |
| 734 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, |
| 735 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), |
| 736 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, |
| 737 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), |
| 738 |
| 739 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, |
| 740 9, 0), |
| 741 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, |
| 742 8, 0), |
| 743 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, |
| 744 0, 0), |
| 745 |
| 746 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, |
| 747 11, 0), |
| 748 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, |
| 749 10, 0), |
| 750 |
| 751 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, |
| 752 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), |
| 753 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, |
| 754 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), |
| 755 |
| 756 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), |
| 757 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), |
| 758 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), |
| 759 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), |
| 760 |
| 761 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, |
| 762 ARRAY_SIZE(dac1l_mix)), |
| 763 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, |
| 764 ARRAY_SIZE(dac1r_mix)), |
| 765 |
| 766 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), |
| 767 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), |
| 768 |
| 769 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, |
| 770 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 771 |
| 772 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, |
| 773 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), |
| 774 |
| 775 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, |
| 776 4, 0, &spk1l_mux), |
| 777 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, |
| 778 4, 0, &spk1r_mux), |
| 779 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, |
| 780 4, 0, &spk2l_mux), |
| 781 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, |
| 782 4, 0, &spk2r_mux), |
| 783 |
| 784 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), |
| 785 |
| 786 SND_SOC_DAPM_OUTPUT("HP1L"), |
| 787 SND_SOC_DAPM_OUTPUT("HP1R"), |
| 788 SND_SOC_DAPM_OUTPUT("SPK1L"), |
| 789 SND_SOC_DAPM_OUTPUT("SPK1R"), |
| 790 SND_SOC_DAPM_OUTPUT("SPK2L"), |
| 791 SND_SOC_DAPM_OUTPUT("SPK2R") |
| 792 }; |
| 793 |
| 794 static const struct snd_soc_dapm_route wm8995_intercon[] = { |
| 795 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, |
| 796 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, |
| 797 |
| 798 { "DSP1CLK", NULL, "CLK_SYS" }, |
| 799 { "DSP2CLK", NULL, "CLK_SYS" }, |
| 800 { "SYSDSPCLK", NULL, "CLK_SYS" }, |
| 801 |
| 802 { "AIF1ADC1L", NULL, "AIF1CLK" }, |
| 803 { "AIF1ADC1L", NULL, "DSP1CLK" }, |
| 804 { "AIF1ADC1R", NULL, "AIF1CLK" }, |
| 805 { "AIF1ADC1R", NULL, "DSP1CLK" }, |
| 806 { "AIF1ADC1R", NULL, "SYSDSPCLK" }, |
| 807 |
| 808 { "AIF1ADC2L", NULL, "AIF1CLK" }, |
| 809 { "AIF1ADC2L", NULL, "DSP1CLK" }, |
| 810 { "AIF1ADC2R", NULL, "AIF1CLK" }, |
| 811 { "AIF1ADC2R", NULL, "DSP1CLK" }, |
| 812 { "AIF1ADC2R", NULL, "SYSDSPCLK" }, |
| 813 |
| 814 { "DMIC1L", NULL, "DMIC1DAT" }, |
| 815 { "DMIC1L", NULL, "CLK_SYS" }, |
| 816 { "DMIC1R", NULL, "DMIC1DAT" }, |
| 817 { "DMIC1R", NULL, "CLK_SYS" }, |
| 818 { "DMIC2L", NULL, "DMIC2DAT" }, |
| 819 { "DMIC2L", NULL, "CLK_SYS" }, |
| 820 { "DMIC2R", NULL, "DMIC2DAT" }, |
| 821 { "DMIC2R", NULL, "CLK_SYS" }, |
| 822 |
| 823 { "ADCL", NULL, "AIF1CLK" }, |
| 824 { "ADCL", NULL, "DSP1CLK" }, |
| 825 { "ADCL", NULL, "SYSDSPCLK" }, |
| 826 |
| 827 { "ADCR", NULL, "AIF1CLK" }, |
| 828 { "ADCR", NULL, "DSP1CLK" }, |
| 829 { "ADCR", NULL, "SYSDSPCLK" }, |
| 830 |
| 831 { "IN1L PGA", "IN1L Switch", "IN1L" }, |
| 832 { "IN1R PGA", "IN1R Switch", "IN1R" }, |
| 833 { "IN1L PGA", NULL, "LDO2" }, |
| 834 { "IN1R PGA", NULL, "LDO2" }, |
| 835 |
| 836 { "ADCL", NULL, "IN1L PGA" }, |
| 837 { "ADCR", NULL, "IN1R PGA" }, |
| 838 |
| 839 { "ADCL Mux", "ADC", "ADCL" }, |
| 840 { "ADCL Mux", "DMIC", "DMIC1L" }, |
| 841 { "ADCR Mux", "ADC", "ADCR" }, |
| 842 { "ADCR Mux", "DMIC", "DMIC1R" }, |
| 843 |
| 844 /* AIF1 outputs */ |
| 845 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, |
| 846 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, |
| 847 |
| 848 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, |
| 849 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, |
| 850 |
| 851 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, |
| 852 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, |
| 853 |
| 854 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, |
| 855 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, |
| 856 |
| 857 /* Sidetone */ |
| 858 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, |
| 859 { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, |
| 860 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, |
| 861 { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, |
| 862 |
| 863 { "AIF1DAC1L", NULL, "AIF1CLK" }, |
| 864 { "AIF1DAC1L", NULL, "DSP1CLK" }, |
| 865 { "AIF1DAC1R", NULL, "AIF1CLK" }, |
| 866 { "AIF1DAC1R", NULL, "DSP1CLK" }, |
| 867 { "AIF1DAC1R", NULL, "SYSDSPCLK" }, |
| 868 |
| 869 { "AIF1DAC2L", NULL, "AIF1CLK" }, |
| 870 { "AIF1DAC2L", NULL, "DSP1CLK" }, |
| 871 { "AIF1DAC2R", NULL, "AIF1CLK" }, |
| 872 { "AIF1DAC2R", NULL, "DSP1CLK" }, |
| 873 { "AIF1DAC2R", NULL, "SYSDSPCLK" }, |
| 874 |
| 875 { "DAC1L", NULL, "AIF1CLK" }, |
| 876 { "DAC1L", NULL, "DSP1CLK" }, |
| 877 { "DAC1L", NULL, "SYSDSPCLK" }, |
| 878 |
| 879 { "DAC1R", NULL, "AIF1CLK" }, |
| 880 { "DAC1R", NULL, "DSP1CLK" }, |
| 881 { "DAC1R", NULL, "SYSDSPCLK" }, |
| 882 |
| 883 { "AIF1DAC1L", NULL, "AIF1DACDAT" }, |
| 884 { "AIF1DAC1R", NULL, "AIF1DACDAT" }, |
| 885 { "AIF1DAC2L", NULL, "AIF1DACDAT" }, |
| 886 { "AIF1DAC2R", NULL, "AIF1DACDAT" }, |
| 887 |
| 888 /* DAC1 inputs */ |
| 889 { "DAC1L", NULL, "DAC1L Mixer" }, |
| 890 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, |
| 891 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, |
| 892 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, |
| 893 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, |
| 894 |
| 895 { "DAC1R", NULL, "DAC1R Mixer" }, |
| 896 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, |
| 897 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, |
| 898 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, |
| 899 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, |
| 900 |
| 901 /* DAC2/AIF2 outputs */ |
| 902 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, |
| 903 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, |
| 904 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, |
| 905 |
| 906 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, |
| 907 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, |
| 908 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, |
| 909 |
| 910 /* Output stages */ |
| 911 { "Headphone PGA", NULL, "DAC1L" }, |
| 912 { "Headphone PGA", NULL, "DAC1R" }, |
| 913 |
| 914 { "Headphone PGA", NULL, "DAC2L" }, |
| 915 { "Headphone PGA", NULL, "DAC2R" }, |
| 916 |
| 917 { "Headphone PGA", NULL, "Headphone Supply" }, |
| 918 { "Headphone PGA", NULL, "CLK_SYS" }, |
| 919 { "Headphone PGA", NULL, "LDO2" }, |
| 920 |
| 921 { "HP1L", NULL, "Headphone PGA" }, |
| 922 { "HP1R", NULL, "Headphone PGA" }, |
| 923 |
| 924 { "SPK1L Driver", "DAC1L", "DAC1L" }, |
| 925 { "SPK1L Driver", "DAC1R", "DAC1R" }, |
| 926 { "SPK1L Driver", "DAC2L", "DAC2L" }, |
| 927 { "SPK1L Driver", "DAC2R", "DAC2R" }, |
| 928 { "SPK1L Driver", NULL, "CLK_SYS" }, |
| 929 |
| 930 { "SPK1R Driver", "DAC1L", "DAC1L" }, |
| 931 { "SPK1R Driver", "DAC1R", "DAC1R" }, |
| 932 { "SPK1R Driver", "DAC2L", "DAC2L" }, |
| 933 { "SPK1R Driver", "DAC2R", "DAC2R" }, |
| 934 { "SPK1R Driver", NULL, "CLK_SYS" }, |
| 935 |
| 936 { "SPK2L Driver", "DAC1L", "DAC1L" }, |
| 937 { "SPK2L Driver", "DAC1R", "DAC1R" }, |
| 938 { "SPK2L Driver", "DAC2L", "DAC2L" }, |
| 939 { "SPK2L Driver", "DAC2R", "DAC2R" }, |
| 940 { "SPK2L Driver", NULL, "CLK_SYS" }, |
| 941 |
| 942 { "SPK2R Driver", "DAC1L", "DAC1L" }, |
| 943 { "SPK2R Driver", "DAC1R", "DAC1R" }, |
| 944 { "SPK2R Driver", "DAC2L", "DAC2L" }, |
| 945 { "SPK2R Driver", "DAC2R", "DAC2R" }, |
| 946 { "SPK2R Driver", NULL, "CLK_SYS" }, |
| 947 |
| 948 { "SPK1L", NULL, "SPK1L Driver" }, |
| 949 { "SPK1R", NULL, "SPK1R Driver" }, |
| 950 { "SPK2L", NULL, "SPK2L Driver" }, |
| 951 { "SPK2R", NULL, "SPK2R Driver" } |
| 952 }; |
| 953 |
| 954 static int wm8995_volatile(struct snd_soc_codec *codec, unsigned int reg) |
| 955 { |
| 956 /* out of bounds registers are generally considered |
| 957 * volatile to support register banks that are partially |
| 958 * owned by something else for e.g. a DSP |
| 959 */ |
| 960 if (reg > WM8995_MAX_CACHED_REGISTER) |
| 961 return 1; |
| 962 |
| 963 switch (reg) { |
| 964 case WM8995_SOFTWARE_RESET: |
| 965 case WM8995_DC_SERVO_READBACK_0: |
| 966 case WM8995_INTERRUPT_STATUS_1: |
| 967 case WM8995_INTERRUPT_STATUS_2: |
| 968 case WM8995_INTERRUPT_STATUS_1_MASK: |
| 969 case WM8995_INTERRUPT_STATUS_2_MASK: |
| 970 case WM8995_INTERRUPT_CONTROL: |
| 971 case WM8995_ACCESSORY_DETECT_MODE1: |
| 972 case WM8995_ACCESSORY_DETECT_MODE2: |
| 973 case WM8995_HEADPHONE_DETECT1: |
| 974 case WM8995_HEADPHONE_DETECT2: |
| 975 return 1; |
| 976 } |
| 977 |
| 978 return 0; |
| 979 } |
| 980 |
| 981 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) |
| 982 { |
| 983 struct snd_soc_codec *codec = dai->codec; |
| 984 int mute_reg; |
| 985 |
| 986 switch (dai->id) { |
| 987 case 0: |
| 988 mute_reg = WM8995_AIF1_DAC1_FILTERS_1; |
| 989 break; |
| 990 case 1: |
| 991 mute_reg = WM8995_AIF2_DAC_FILTERS_1; |
| 992 break; |
| 993 default: |
| 994 return -EINVAL; |
| 995 } |
| 996 |
| 997 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, |
| 998 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); |
| 999 return 0; |
| 1000 } |
| 1001 |
| 1002 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 1003 { |
| 1004 struct snd_soc_codec *codec; |
| 1005 int master; |
| 1006 int aif; |
| 1007 |
| 1008 codec = dai->codec; |
| 1009 |
| 1010 master = 0; |
| 1011 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1012 case SND_SOC_DAIFMT_CBS_CFS: |
| 1013 break; |
| 1014 case SND_SOC_DAIFMT_CBM_CFM: |
| 1015 master = WM8995_AIF1_MSTR; |
| 1016 break; |
| 1017 default: |
| 1018 dev_err(dai->dev, "Unknown master/slave configuration\n"); |
| 1019 return -EINVAL; |
| 1020 } |
| 1021 |
| 1022 aif = 0; |
| 1023 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1024 case SND_SOC_DAIFMT_DSP_B: |
| 1025 aif |= WM8995_AIF1_LRCLK_INV; |
| 1026 case SND_SOC_DAIFMT_DSP_A: |
| 1027 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); |
| 1028 break; |
| 1029 case SND_SOC_DAIFMT_I2S: |
| 1030 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); |
| 1031 break; |
| 1032 case SND_SOC_DAIFMT_RIGHT_J: |
| 1033 break; |
| 1034 case SND_SOC_DAIFMT_LEFT_J: |
| 1035 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); |
| 1036 break; |
| 1037 default: |
| 1038 dev_err(dai->dev, "Unknown dai format\n"); |
| 1039 return -EINVAL; |
| 1040 } |
| 1041 |
| 1042 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1043 case SND_SOC_DAIFMT_DSP_A: |
| 1044 case SND_SOC_DAIFMT_DSP_B: |
| 1045 /* frame inversion not valid for DSP modes */ |
| 1046 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1047 case SND_SOC_DAIFMT_NB_NF: |
| 1048 break; |
| 1049 case SND_SOC_DAIFMT_IB_NF: |
| 1050 aif |= WM8995_AIF1_BCLK_INV; |
| 1051 break; |
| 1052 default: |
| 1053 return -EINVAL; |
| 1054 } |
| 1055 break; |
| 1056 |
| 1057 case SND_SOC_DAIFMT_I2S: |
| 1058 case SND_SOC_DAIFMT_RIGHT_J: |
| 1059 case SND_SOC_DAIFMT_LEFT_J: |
| 1060 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1061 case SND_SOC_DAIFMT_NB_NF: |
| 1062 break; |
| 1063 case SND_SOC_DAIFMT_IB_IF: |
| 1064 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; |
| 1065 break; |
| 1066 case SND_SOC_DAIFMT_IB_NF: |
| 1067 aif |= WM8995_AIF1_BCLK_INV; |
| 1068 break; |
| 1069 case SND_SOC_DAIFMT_NB_IF: |
| 1070 aif |= WM8995_AIF1_LRCLK_INV; |
| 1071 break; |
| 1072 default: |
| 1073 return -EINVAL; |
| 1074 } |
| 1075 break; |
| 1076 default: |
| 1077 return -EINVAL; |
| 1078 } |
| 1079 |
| 1080 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, |
| 1081 WM8995_AIF1_BCLK_INV_MASK | |
| 1082 WM8995_AIF1_LRCLK_INV_MASK | |
| 1083 WM8995_AIF1_FMT_MASK, aif); |
| 1084 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, |
| 1085 WM8995_AIF1_MSTR_MASK, master); |
| 1086 return 0; |
| 1087 } |
| 1088 |
| 1089 static const int srs[] = { |
| 1090 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, |
| 1091 48000, 88200, 96000 |
| 1092 }; |
| 1093 |
| 1094 static const int fs_ratios[] = { |
| 1095 -1 /* reserved */, |
| 1096 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 |
| 1097 }; |
| 1098 |
| 1099 static const int bclk_divs[] = { |
| 1100 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 |
| 1101 }; |
| 1102 |
| 1103 static int wm8995_hw_params(struct snd_pcm_substream *substream, |
| 1104 struct snd_pcm_hw_params *params, |
| 1105 struct snd_soc_dai *dai) |
| 1106 { |
| 1107 struct snd_soc_codec *codec; |
| 1108 struct wm8995_priv *wm8995; |
| 1109 int aif1_reg; |
| 1110 int bclk_reg; |
| 1111 int lrclk_reg; |
| 1112 int rate_reg; |
| 1113 int bclk_rate; |
| 1114 int aif1; |
| 1115 int lrclk, bclk; |
| 1116 int i, rate_val, best, best_val, cur_val; |
| 1117 |
| 1118 codec = dai->codec; |
| 1119 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1120 |
| 1121 switch (dai->id) { |
| 1122 case 0: |
| 1123 aif1_reg = WM8995_AIF1_CONTROL_1; |
| 1124 bclk_reg = WM8995_AIF1_BCLK; |
| 1125 rate_reg = WM8995_AIF1_RATE; |
| 1126 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || |
| 1127 wm8995->lrclk_shared[0] */) { |
| 1128 lrclk_reg = WM8995_AIF1DAC_LRCLK; |
| 1129 } else { |
| 1130 lrclk_reg = WM8995_AIF1ADC_LRCLK; |
| 1131 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); |
| 1132 } |
| 1133 break; |
| 1134 case 1: |
| 1135 aif1_reg = WM8995_AIF2_CONTROL_1; |
| 1136 bclk_reg = WM8995_AIF2_BCLK; |
| 1137 rate_reg = WM8995_AIF2_RATE; |
| 1138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || |
| 1139 wm8995->lrclk_shared[1] */) { |
| 1140 lrclk_reg = WM8995_AIF2DAC_LRCLK; |
| 1141 } else { |
| 1142 lrclk_reg = WM8995_AIF2ADC_LRCLK; |
| 1143 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); |
| 1144 } |
| 1145 break; |
| 1146 default: |
| 1147 return -EINVAL; |
| 1148 } |
| 1149 |
| 1150 bclk_rate = snd_soc_params_to_bclk(params); |
| 1151 if (bclk_rate < 0) |
| 1152 return bclk_rate; |
| 1153 |
| 1154 aif1 = 0; |
| 1155 switch (params_format(params)) { |
| 1156 case SNDRV_PCM_FORMAT_S16_LE: |
| 1157 break; |
| 1158 case SNDRV_PCM_FORMAT_S20_3LE: |
| 1159 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); |
| 1160 break; |
| 1161 case SNDRV_PCM_FORMAT_S24_LE: |
| 1162 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); |
| 1163 break; |
| 1164 case SNDRV_PCM_FORMAT_S32_LE: |
| 1165 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); |
| 1166 break; |
| 1167 default: |
| 1168 dev_err(dai->dev, "Unsupported word length %u\n", |
| 1169 params_format(params)); |
| 1170 return -EINVAL; |
| 1171 } |
| 1172 |
| 1173 /* try to find a suitable sample rate */ |
| 1174 for (i = 0; i < ARRAY_SIZE(srs); ++i) |
| 1175 if (srs[i] == params_rate(params)) |
| 1176 break; |
| 1177 if (i == ARRAY_SIZE(srs)) { |
| 1178 dev_err(dai->dev, "Sample rate %d is not supported\n", |
| 1179 params_rate(params)); |
| 1180 return -EINVAL; |
| 1181 } |
| 1182 rate_val = i << WM8995_AIF1_SR_SHIFT; |
| 1183 |
| 1184 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); |
| 1185 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", |
| 1186 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); |
| 1187 |
| 1188 /* AIFCLK/fs ratio; look for a close match in either direction */ |
| 1189 best = 1; |
| 1190 best_val = abs((fs_ratios[1] * params_rate(params)) |
| 1191 - wm8995->aifclk[dai->id]); |
| 1192 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { |
| 1193 cur_val = abs((fs_ratios[i] * params_rate(params)) |
| 1194 - wm8995->aifclk[dai->id]); |
| 1195 if (cur_val >= best_val) |
| 1196 continue; |
| 1197 best = i; |
| 1198 best_val = cur_val; |
| 1199 } |
| 1200 rate_val |= best; |
| 1201 |
| 1202 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", |
| 1203 dai->id + 1, fs_ratios[best]); |
| 1204 |
| 1205 /* |
| 1206 * We may not get quite the right frequency if using |
| 1207 * approximate clocks so look for the closest match that is |
| 1208 * higher than the target (we need to ensure that there enough |
| 1209 * BCLKs to clock out the samples). |
| 1210 */ |
| 1211 best = 0; |
| 1212 bclk = 0; |
| 1213 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { |
| 1214 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_r
ate; |
| 1215 if (cur_val < 0) /* BCLK table is sorted */ |
| 1216 break; |
| 1217 best = i; |
| 1218 } |
| 1219 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; |
| 1220 |
| 1221 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; |
| 1222 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", |
| 1223 bclk_divs[best], bclk_rate); |
| 1224 |
| 1225 lrclk = bclk_rate / params_rate(params); |
| 1226 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", |
| 1227 lrclk, bclk_rate / lrclk); |
| 1228 |
| 1229 snd_soc_update_bits(codec, aif1_reg, |
| 1230 WM8995_AIF1_WL_MASK, aif1); |
| 1231 snd_soc_update_bits(codec, bclk_reg, |
| 1232 WM8995_AIF1_BCLK_DIV_MASK, bclk); |
| 1233 snd_soc_update_bits(codec, lrclk_reg, |
| 1234 WM8995_AIF1DAC_RATE_MASK, lrclk); |
| 1235 snd_soc_update_bits(codec, rate_reg, |
| 1236 WM8995_AIF1_SR_MASK | |
| 1237 WM8995_AIF1CLK_RATE_MASK, rate_val); |
| 1238 return 0; |
| 1239 } |
| 1240 |
| 1241 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) |
| 1242 { |
| 1243 struct snd_soc_codec *codec = codec_dai->codec; |
| 1244 int reg, val, mask; |
| 1245 |
| 1246 switch (codec_dai->id) { |
| 1247 case 0: |
| 1248 reg = WM8995_AIF1_MASTER_SLAVE; |
| 1249 mask = WM8995_AIF1_TRI; |
| 1250 break; |
| 1251 case 1: |
| 1252 reg = WM8995_AIF2_MASTER_SLAVE; |
| 1253 mask = WM8995_AIF2_TRI; |
| 1254 break; |
| 1255 case 2: |
| 1256 reg = WM8995_POWER_MANAGEMENT_5; |
| 1257 mask = WM8995_AIF3_TRI; |
| 1258 break; |
| 1259 default: |
| 1260 return -EINVAL; |
| 1261 } |
| 1262 |
| 1263 if (tristate) |
| 1264 val = mask; |
| 1265 else |
| 1266 val = 0; |
| 1267 |
| 1268 return snd_soc_update_bits(codec, reg, mask, val); |
| 1269 } |
| 1270 |
| 1271 /* The size in bits of the FLL divide multiplied by 10 |
| 1272 * to allow rounding later */ |
| 1273 #define FIXED_FLL_SIZE ((1 << 16) * 10) |
| 1274 |
| 1275 struct fll_div { |
| 1276 u16 outdiv; |
| 1277 u16 n; |
| 1278 u16 k; |
| 1279 u16 clk_ref_div; |
| 1280 u16 fll_fratio; |
| 1281 }; |
| 1282 |
| 1283 static int wm8995_get_fll_config(struct fll_div *fll, |
| 1284 int freq_in, int freq_out) |
| 1285 { |
| 1286 u64 Kpart; |
| 1287 unsigned int K, Ndiv, Nmod; |
| 1288 |
| 1289 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); |
| 1290 |
| 1291 /* Scale the input frequency down to <= 13.5MHz */ |
| 1292 fll->clk_ref_div = 0; |
| 1293 while (freq_in > 13500000) { |
| 1294 fll->clk_ref_div++; |
| 1295 freq_in /= 2; |
| 1296 |
| 1297 if (fll->clk_ref_div > 3) |
| 1298 return -EINVAL; |
| 1299 } |
| 1300 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); |
| 1301 |
| 1302 /* Scale the output to give 90MHz<=Fvco<=100MHz */ |
| 1303 fll->outdiv = 3; |
| 1304 while (freq_out * (fll->outdiv + 1) < 90000000) { |
| 1305 fll->outdiv++; |
| 1306 if (fll->outdiv > 63) |
| 1307 return -EINVAL; |
| 1308 } |
| 1309 freq_out *= fll->outdiv + 1; |
| 1310 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); |
| 1311 |
| 1312 if (freq_in > 1000000) { |
| 1313 fll->fll_fratio = 0; |
| 1314 } else if (freq_in > 256000) { |
| 1315 fll->fll_fratio = 1; |
| 1316 freq_in *= 2; |
| 1317 } else if (freq_in > 128000) { |
| 1318 fll->fll_fratio = 2; |
| 1319 freq_in *= 4; |
| 1320 } else if (freq_in > 64000) { |
| 1321 fll->fll_fratio = 3; |
| 1322 freq_in *= 8; |
| 1323 } else { |
| 1324 fll->fll_fratio = 4; |
| 1325 freq_in *= 16; |
| 1326 } |
| 1327 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); |
| 1328 |
| 1329 /* Now, calculate N.K */ |
| 1330 Ndiv = freq_out / freq_in; |
| 1331 |
| 1332 fll->n = Ndiv; |
| 1333 Nmod = freq_out % freq_in; |
| 1334 pr_debug("Nmod=%d\n", Nmod); |
| 1335 |
| 1336 /* Calculate fractional part - scale up so we can round. */ |
| 1337 Kpart = FIXED_FLL_SIZE * (long long)Nmod; |
| 1338 |
| 1339 do_div(Kpart, freq_in); |
| 1340 |
| 1341 K = Kpart & 0xFFFFFFFF; |
| 1342 |
| 1343 if ((K % 10) >= 5) |
| 1344 K += 5; |
| 1345 |
| 1346 /* Move down to proper range now rounding is done */ |
| 1347 fll->k = K / 10; |
| 1348 |
| 1349 pr_debug("N=%x K=%x\n", fll->n, fll->k); |
| 1350 |
| 1351 return 0; |
| 1352 } |
| 1353 |
| 1354 static int wm8995_set_fll(struct snd_soc_dai *dai, int id, |
| 1355 int src, unsigned int freq_in, |
| 1356 unsigned int freq_out) |
| 1357 { |
| 1358 struct snd_soc_codec *codec; |
| 1359 struct wm8995_priv *wm8995; |
| 1360 int reg_offset, ret; |
| 1361 struct fll_div fll; |
| 1362 u16 reg, aif1, aif2; |
| 1363 |
| 1364 codec = dai->codec; |
| 1365 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1366 |
| 1367 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) |
| 1368 & WM8995_AIF1CLK_ENA; |
| 1369 |
| 1370 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) |
| 1371 & WM8995_AIF2CLK_ENA; |
| 1372 |
| 1373 switch (id) { |
| 1374 case WM8995_FLL1: |
| 1375 reg_offset = 0; |
| 1376 id = 0; |
| 1377 break; |
| 1378 case WM8995_FLL2: |
| 1379 reg_offset = 0x20; |
| 1380 id = 1; |
| 1381 break; |
| 1382 default: |
| 1383 return -EINVAL; |
| 1384 } |
| 1385 |
| 1386 switch (src) { |
| 1387 case 0: |
| 1388 /* Allow no source specification when stopping */ |
| 1389 if (freq_out) |
| 1390 return -EINVAL; |
| 1391 break; |
| 1392 case WM8995_FLL_SRC_MCLK1: |
| 1393 case WM8995_FLL_SRC_MCLK2: |
| 1394 case WM8995_FLL_SRC_LRCLK: |
| 1395 case WM8995_FLL_SRC_BCLK: |
| 1396 break; |
| 1397 default: |
| 1398 return -EINVAL; |
| 1399 } |
| 1400 |
| 1401 /* Are we changing anything? */ |
| 1402 if (wm8995->fll[id].src == src && |
| 1403 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) |
| 1404 return 0; |
| 1405 |
| 1406 /* If we're stopping the FLL redo the old config - no |
| 1407 * registers will actually be written but we avoid GCC flow |
| 1408 * analysis bugs spewing warnings. |
| 1409 */ |
| 1410 if (freq_out) |
| 1411 ret = wm8995_get_fll_config(&fll, freq_in, freq_out); |
| 1412 else |
| 1413 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, |
| 1414 wm8995->fll[id].out); |
| 1415 if (ret < 0) |
| 1416 return ret; |
| 1417 |
| 1418 /* Gate the AIF clocks while we reclock */ |
| 1419 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, |
| 1420 WM8995_AIF1CLK_ENA_MASK, 0); |
| 1421 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, |
| 1422 WM8995_AIF2CLK_ENA_MASK, 0); |
| 1423 |
| 1424 /* We always need to disable the FLL while reconfiguring */ |
| 1425 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, |
| 1426 WM8995_FLL1_ENA_MASK, 0); |
| 1427 |
| 1428 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | |
| 1429 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); |
| 1430 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, |
| 1431 WM8995_FLL1_OUTDIV_MASK | |
| 1432 WM8995_FLL1_FRATIO_MASK, reg); |
| 1433 |
| 1434 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); |
| 1435 |
| 1436 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, |
| 1437 WM8995_FLL1_N_MASK, |
| 1438 fll.n << WM8995_FLL1_N_SHIFT); |
| 1439 |
| 1440 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, |
| 1441 WM8995_FLL1_REFCLK_DIV_MASK | |
| 1442 WM8995_FLL1_REFCLK_SRC_MASK, |
| 1443 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | |
| 1444 (src - 1)); |
| 1445 |
| 1446 if (freq_out) |
| 1447 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, |
| 1448 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); |
| 1449 |
| 1450 wm8995->fll[id].in = freq_in; |
| 1451 wm8995->fll[id].out = freq_out; |
| 1452 wm8995->fll[id].src = src; |
| 1453 |
| 1454 /* Enable any gated AIF clocks */ |
| 1455 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, |
| 1456 WM8995_AIF1CLK_ENA_MASK, aif1); |
| 1457 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, |
| 1458 WM8995_AIF2CLK_ENA_MASK, aif2); |
| 1459 |
| 1460 configure_clock(codec); |
| 1461 |
| 1462 return 0; |
| 1463 } |
| 1464 |
| 1465 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, |
| 1466 int clk_id, unsigned int freq, int dir) |
| 1467 { |
| 1468 struct snd_soc_codec *codec; |
| 1469 struct wm8995_priv *wm8995; |
| 1470 |
| 1471 codec = dai->codec; |
| 1472 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1473 |
| 1474 switch (dai->id) { |
| 1475 case 0: |
| 1476 case 1: |
| 1477 break; |
| 1478 default: |
| 1479 /* AIF3 shares clocking with AIF1/2 */ |
| 1480 return -EINVAL; |
| 1481 } |
| 1482 |
| 1483 switch (clk_id) { |
| 1484 case WM8995_SYSCLK_MCLK1: |
| 1485 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; |
| 1486 wm8995->mclk[0] = freq; |
| 1487 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", |
| 1488 dai->id + 1, freq); |
| 1489 break; |
| 1490 case WM8995_SYSCLK_MCLK2: |
| 1491 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; |
| 1492 wm8995->mclk[1] = freq; |
| 1493 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", |
| 1494 dai->id + 1, freq); |
| 1495 break; |
| 1496 case WM8995_SYSCLK_FLL1: |
| 1497 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; |
| 1498 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); |
| 1499 break; |
| 1500 case WM8995_SYSCLK_FLL2: |
| 1501 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; |
| 1502 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); |
| 1503 break; |
| 1504 case WM8995_SYSCLK_OPCLK: |
| 1505 default: |
| 1506 dev_err(dai->dev, "Unknown clock source %d\n", clk_id); |
| 1507 return -EINVAL; |
| 1508 } |
| 1509 |
| 1510 configure_clock(codec); |
| 1511 |
| 1512 return 0; |
| 1513 } |
| 1514 |
| 1515 static int wm8995_set_bias_level(struct snd_soc_codec *codec, |
| 1516 enum snd_soc_bias_level level) |
| 1517 { |
| 1518 struct wm8995_priv *wm8995; |
| 1519 int ret; |
| 1520 |
| 1521 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1522 switch (level) { |
| 1523 case SND_SOC_BIAS_ON: |
| 1524 case SND_SOC_BIAS_PREPARE: |
| 1525 break; |
| 1526 case SND_SOC_BIAS_STANDBY: |
| 1527 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
| 1528 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies)
, |
| 1529 wm8995->supplies); |
| 1530 if (ret) |
| 1531 return ret; |
| 1532 |
| 1533 ret = snd_soc_cache_sync(codec); |
| 1534 if (ret) { |
| 1535 dev_err(codec->dev, |
| 1536 "Failed to sync cache: %d\n", ret); |
| 1537 return ret; |
| 1538 } |
| 1539 |
| 1540 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, |
| 1541 WM8995_BG_ENA_MASK, WM8995_BG_ENA); |
| 1542 } |
| 1543 break; |
| 1544 case SND_SOC_BIAS_OFF: |
| 1545 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, |
| 1546 WM8995_BG_ENA_MASK, 0); |
| 1547 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), |
| 1548 wm8995->supplies); |
| 1549 break; |
| 1550 } |
| 1551 |
| 1552 codec->dapm.bias_level = level; |
| 1553 return 0; |
| 1554 } |
| 1555 |
| 1556 #ifdef CONFIG_PM |
| 1557 static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state) |
| 1558 { |
| 1559 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1560 return 0; |
| 1561 } |
| 1562 |
| 1563 static int wm8995_resume(struct snd_soc_codec *codec) |
| 1564 { |
| 1565 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1566 return 0; |
| 1567 } |
| 1568 #else |
| 1569 #define wm8995_suspend NULL |
| 1570 #define wm8995_resume NULL |
| 1571 #endif |
| 1572 |
| 1573 static int wm8995_remove(struct snd_soc_codec *codec) |
| 1574 { |
| 1575 struct wm8995_priv *wm8995; |
| 1576 struct i2c_client *i2c; |
| 1577 |
| 1578 i2c = container_of(codec->dev, struct i2c_client, dev); |
| 1579 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1580 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1581 return 0; |
| 1582 } |
| 1583 |
| 1584 static int wm8995_probe(struct snd_soc_codec *codec) |
| 1585 { |
| 1586 struct wm8995_priv *wm8995; |
| 1587 int i; |
| 1588 int ret; |
| 1589 |
| 1590 codec->dapm.idle_bias_off = 1; |
| 1591 wm8995 = snd_soc_codec_get_drvdata(codec); |
| 1592 wm8995->codec = codec; |
| 1593 |
| 1594 ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type); |
| 1595 if (ret < 0) { |
| 1596 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); |
| 1597 return ret; |
| 1598 } |
| 1599 |
| 1600 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) |
| 1601 wm8995->supplies[i].supply = wm8995_supply_names[i]; |
| 1602 |
| 1603 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies), |
| 1604 wm8995->supplies); |
| 1605 if (ret) { |
| 1606 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); |
| 1607 return ret; |
| 1608 } |
| 1609 |
| 1610 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; |
| 1611 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; |
| 1612 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; |
| 1613 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; |
| 1614 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; |
| 1615 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; |
| 1616 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; |
| 1617 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; |
| 1618 |
| 1619 /* This should really be moved into the regulator core */ |
| 1620 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { |
| 1621 ret = regulator_register_notifier(wm8995->supplies[i].consumer, |
| 1622 &wm8995->disable_nb[i]); |
| 1623 if (ret) { |
| 1624 dev_err(codec->dev, |
| 1625 "Failed to register regulator notifier: %d\n", |
| 1626 ret); |
| 1627 } |
| 1628 } |
| 1629 |
| 1630 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), |
| 1631 wm8995->supplies); |
| 1632 if (ret) { |
| 1633 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); |
| 1634 goto err_reg_get; |
| 1635 } |
| 1636 |
| 1637 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); |
| 1638 if (ret < 0) { |
| 1639 dev_err(codec->dev, "Failed to read device ID: %d\n", ret); |
| 1640 goto err_reg_enable; |
| 1641 } |
| 1642 |
| 1643 if (ret != 0x8995) { |
| 1644 dev_err(codec->dev, "Invalid device ID: %#x\n", ret); |
| 1645 goto err_reg_enable; |
| 1646 } |
| 1647 |
| 1648 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); |
| 1649 if (ret < 0) { |
| 1650 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); |
| 1651 goto err_reg_enable; |
| 1652 } |
| 1653 |
| 1654 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1655 |
| 1656 /* Latch volume updates (right only; we always do left then right). */ |
| 1657 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, |
| 1658 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); |
| 1659 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, |
| 1660 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); |
| 1661 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, |
| 1662 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); |
| 1663 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, |
| 1664 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); |
| 1665 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, |
| 1666 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); |
| 1667 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, |
| 1668 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); |
| 1669 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, |
| 1670 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); |
| 1671 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, |
| 1672 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); |
| 1673 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, |
| 1674 WM8995_IN1_VU_MASK, WM8995_IN1_VU); |
| 1675 |
| 1676 wm8995_update_class_w(codec); |
| 1677 |
| 1678 snd_soc_add_controls(codec, wm8995_snd_controls, |
| 1679 ARRAY_SIZE(wm8995_snd_controls)); |
| 1680 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, |
| 1681 ARRAY_SIZE(wm8995_dapm_widgets)); |
| 1682 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, |
| 1683 ARRAY_SIZE(wm8995_intercon)); |
| 1684 |
| 1685 return 0; |
| 1686 |
| 1687 err_reg_enable: |
| 1688 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); |
| 1689 err_reg_get: |
| 1690 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); |
| 1691 return ret; |
| 1692 } |
| 1693 |
| 1694 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 1695 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 1696 |
| 1697 static struct snd_soc_dai_ops wm8995_aif1_dai_ops = { |
| 1698 .set_sysclk = wm8995_set_dai_sysclk, |
| 1699 .set_fmt = wm8995_set_dai_fmt, |
| 1700 .hw_params = wm8995_hw_params, |
| 1701 .digital_mute = wm8995_aif_mute, |
| 1702 .set_pll = wm8995_set_fll, |
| 1703 .set_tristate = wm8995_set_tristate, |
| 1704 }; |
| 1705 |
| 1706 static struct snd_soc_dai_ops wm8995_aif2_dai_ops = { |
| 1707 .set_sysclk = wm8995_set_dai_sysclk, |
| 1708 .set_fmt = wm8995_set_dai_fmt, |
| 1709 .hw_params = wm8995_hw_params, |
| 1710 .digital_mute = wm8995_aif_mute, |
| 1711 .set_pll = wm8995_set_fll, |
| 1712 .set_tristate = wm8995_set_tristate, |
| 1713 }; |
| 1714 |
| 1715 static struct snd_soc_dai_ops wm8995_aif3_dai_ops = { |
| 1716 .set_tristate = wm8995_set_tristate, |
| 1717 }; |
| 1718 |
| 1719 static struct snd_soc_dai_driver wm8995_dai[] = { |
| 1720 { |
| 1721 .name = "wm8995-aif1", |
| 1722 .playback = { |
| 1723 .stream_name = "AIF1 Playback", |
| 1724 .channels_min = 2, |
| 1725 .channels_max = 2, |
| 1726 .rates = SNDRV_PCM_RATE_8000_96000, |
| 1727 .formats = WM8995_FORMATS |
| 1728 }, |
| 1729 .capture = { |
| 1730 .stream_name = "AIF1 Capture", |
| 1731 .channels_min = 2, |
| 1732 .channels_max = 2, |
| 1733 .rates = SNDRV_PCM_RATE_8000_48000, |
| 1734 .formats = WM8995_FORMATS |
| 1735 }, |
| 1736 .ops = &wm8995_aif1_dai_ops |
| 1737 }, |
| 1738 { |
| 1739 .name = "wm8995-aif2", |
| 1740 .playback = { |
| 1741 .stream_name = "AIF2 Playback", |
| 1742 .channels_min = 2, |
| 1743 .channels_max = 2, |
| 1744 .rates = SNDRV_PCM_RATE_8000_96000, |
| 1745 .formats = WM8995_FORMATS |
| 1746 }, |
| 1747 .capture = { |
| 1748 .stream_name = "AIF2 Capture", |
| 1749 .channels_min = 2, |
| 1750 .channels_max = 2, |
| 1751 .rates = SNDRV_PCM_RATE_8000_48000, |
| 1752 .formats = WM8995_FORMATS |
| 1753 }, |
| 1754 .ops = &wm8995_aif2_dai_ops |
| 1755 }, |
| 1756 { |
| 1757 .name = "wm8995-aif3", |
| 1758 .playback = { |
| 1759 .stream_name = "AIF3 Playback", |
| 1760 .channels_min = 2, |
| 1761 .channels_max = 2, |
| 1762 .rates = SNDRV_PCM_RATE_8000_96000, |
| 1763 .formats = WM8995_FORMATS |
| 1764 }, |
| 1765 .capture = { |
| 1766 .stream_name = "AIF3 Capture", |
| 1767 .channels_min = 2, |
| 1768 .channels_max = 2, |
| 1769 .rates = SNDRV_PCM_RATE_8000_48000, |
| 1770 .formats = WM8995_FORMATS |
| 1771 }, |
| 1772 .ops = &wm8995_aif3_dai_ops |
| 1773 } |
| 1774 }; |
| 1775 |
| 1776 static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { |
| 1777 .probe = wm8995_probe, |
| 1778 .remove = wm8995_remove, |
| 1779 .suspend = wm8995_suspend, |
| 1780 .resume = wm8995_resume, |
| 1781 .set_bias_level = wm8995_set_bias_level, |
| 1782 .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs), |
| 1783 .reg_word_size = sizeof(u16), |
| 1784 .reg_cache_default = wm8995_reg_defs, |
| 1785 .volatile_register = wm8995_volatile, |
| 1786 .compress_type = SND_SOC_RBTREE_COMPRESSION |
| 1787 }; |
| 1788 |
| 1789 #if defined(CONFIG_SPI_MASTER) |
| 1790 static int __devinit wm8995_spi_probe(struct spi_device *spi) |
| 1791 { |
| 1792 struct wm8995_priv *wm8995; |
| 1793 int ret; |
| 1794 |
| 1795 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); |
| 1796 if (!wm8995) |
| 1797 return -ENOMEM; |
| 1798 |
| 1799 wm8995->control_type = SND_SOC_SPI; |
| 1800 spi_set_drvdata(spi, wm8995); |
| 1801 |
| 1802 ret = snd_soc_register_codec(&spi->dev, |
| 1803 &soc_codec_dev_wm8995, wm8995_dai, |
| 1804 ARRAY_SIZE(wm8995_dai)); |
| 1805 if (ret < 0) |
| 1806 kfree(wm8995); |
| 1807 return ret; |
| 1808 } |
| 1809 |
| 1810 static int __devexit wm8995_spi_remove(struct spi_device *spi) |
| 1811 { |
| 1812 snd_soc_unregister_codec(&spi->dev); |
| 1813 kfree(spi_get_drvdata(spi)); |
| 1814 return 0; |
| 1815 } |
| 1816 |
| 1817 static struct spi_driver wm8995_spi_driver = { |
| 1818 .driver = { |
| 1819 .name = "wm8995", |
| 1820 .owner = THIS_MODULE, |
| 1821 }, |
| 1822 .probe = wm8995_spi_probe, |
| 1823 .remove = __devexit_p(wm8995_spi_remove) |
| 1824 }; |
| 1825 #endif |
| 1826 |
| 1827 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1828 static __devinit int wm8995_i2c_probe(struct i2c_client *i2c, |
| 1829 const struct i2c_device_id *id) |
| 1830 { |
| 1831 struct wm8995_priv *wm8995; |
| 1832 int ret; |
| 1833 |
| 1834 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); |
| 1835 if (!wm8995) |
| 1836 return -ENOMEM; |
| 1837 |
| 1838 wm8995->control_type = SND_SOC_I2C; |
| 1839 i2c_set_clientdata(i2c, wm8995); |
| 1840 |
| 1841 ret = snd_soc_register_codec(&i2c->dev, |
| 1842 &soc_codec_dev_wm8995, wm8995_dai, |
| 1843 ARRAY_SIZE(wm8995_dai)); |
| 1844 if (ret < 0) |
| 1845 kfree(wm8995); |
| 1846 return ret; |
| 1847 } |
| 1848 |
| 1849 static __devexit int wm8995_i2c_remove(struct i2c_client *client) |
| 1850 { |
| 1851 snd_soc_unregister_codec(&client->dev); |
| 1852 kfree(i2c_get_clientdata(client)); |
| 1853 return 0; |
| 1854 } |
| 1855 |
| 1856 static const struct i2c_device_id wm8995_i2c_id[] = { |
| 1857 {"wm8995", 0}, |
| 1858 {} |
| 1859 }; |
| 1860 |
| 1861 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); |
| 1862 |
| 1863 static struct i2c_driver wm8995_i2c_driver = { |
| 1864 .driver = { |
| 1865 .name = "wm8995", |
| 1866 .owner = THIS_MODULE, |
| 1867 }, |
| 1868 .probe = wm8995_i2c_probe, |
| 1869 .remove = __devexit_p(wm8995_i2c_remove), |
| 1870 .id_table = wm8995_i2c_id |
| 1871 }; |
| 1872 #endif |
| 1873 |
| 1874 static int __init wm8995_modinit(void) |
| 1875 { |
| 1876 int ret = 0; |
| 1877 |
| 1878 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1879 ret = i2c_add_driver(&wm8995_i2c_driver); |
| 1880 if (ret) { |
| 1881 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", |
| 1882 ret); |
| 1883 } |
| 1884 #endif |
| 1885 #if defined(CONFIG_SPI_MASTER) |
| 1886 ret = spi_register_driver(&wm8995_spi_driver); |
| 1887 if (ret) { |
| 1888 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", |
| 1889 ret); |
| 1890 } |
| 1891 #endif |
| 1892 return ret; |
| 1893 } |
| 1894 |
| 1895 module_init(wm8995_modinit); |
| 1896 |
| 1897 static void __exit wm8995_exit(void) |
| 1898 { |
| 1899 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1900 i2c_del_driver(&wm8995_i2c_driver); |
| 1901 #endif |
| 1902 #if defined(CONFIG_SPI_MASTER) |
| 1903 spi_unregister_driver(&wm8995_spi_driver); |
| 1904 #endif |
| 1905 } |
| 1906 |
| 1907 module_exit(wm8995_exit); |
| 1908 |
| 1909 MODULE_DESCRIPTION("ASoC WM8995 driver"); |
| 1910 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); |
| 1911 MODULE_LICENSE("GPL"); |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 6577007:
CHROMIUM: ASoC: Import entire upstream ASoC tree (Closed)
