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Side by Side Diff: sound/soc/codecs/wm8994.c

Issue 6577007: CHROMIUM: ASoC: Import entire upstream ASoC tree (Closed)
Patch Set: Created 9 years, 10 months ago
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1 /* 1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver 2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 * 3 *
4 * Copyright 2009 Wolfson Microelectronics plc 4 * Copyright 2009 Wolfson Microelectronics plc
5 * 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * 7 *
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/moduleparam.h> 15 #include <linux/moduleparam.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/delay.h> 17 #include <linux/delay.h>
18 #include <linux/pm.h> 18 #include <linux/pm.h>
19 #include <linux/i2c.h> 19 #include <linux/i2c.h>
20 #include <linux/platform_device.h> 20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h> 22 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h> 23 #include <linux/slab.h>
23 #include <sound/core.h> 24 #include <sound/core.h>
25 #include <sound/jack.h>
24 #include <sound/pcm.h> 26 #include <sound/pcm.h>
25 #include <sound/pcm_params.h> 27 #include <sound/pcm_params.h>
26 #include <sound/soc.h> 28 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h> 29 #include <sound/initval.h>
29 #include <sound/tlv.h> 30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
30 32
31 #include <linux/mfd/wm8994/core.h> 33 #include <linux/mfd/wm8994/core.h>
32 #include <linux/mfd/wm8994/registers.h> 34 #include <linux/mfd/wm8994/registers.h>
33 #include <linux/mfd/wm8994/pdata.h> 35 #include <linux/mfd/wm8994/pdata.h>
34 #include <linux/mfd/wm8994/gpio.h> 36 #include <linux/mfd/wm8994/gpio.h>
35 37
36 #include "wm8994.h" 38 #include "wm8994.h"
37 #include "wm_hubs.h" 39 #include "wm_hubs.h"
38 40
39 struct fll_config { 41 struct fll_config {
(...skipping 10 matching lines...) Expand all
50 WM8994_AIF1_DRC2_1, 52 WM8994_AIF1_DRC2_1,
51 WM8994_AIF2_DRC_1, 53 WM8994_AIF2_DRC_1,
52 }; 54 };
53 55
54 static int wm8994_retune_mobile_base[] = { 56 static int wm8994_retune_mobile_base[] = {
55 WM8994_AIF1_DAC1_EQ_GAINS_1, 57 WM8994_AIF1_DAC1_EQ_GAINS_1,
56 WM8994_AIF1_DAC2_EQ_GAINS_1, 58 WM8994_AIF1_DAC2_EQ_GAINS_1,
57 WM8994_AIF2_EQ_GAINS_1, 59 WM8994_AIF2_EQ_GAINS_1,
58 }; 60 };
59 61
60 #define WM8994_REG_CACHE_SIZE 0x621
61
62 struct wm8994_micdet { 62 struct wm8994_micdet {
63 struct snd_soc_jack *jack; 63 struct snd_soc_jack *jack;
64 int det; 64 int det;
65 int shrt; 65 int shrt;
66 }; 66 };
67 67
68 /* codec private data */ 68 /* codec private data */
69 struct wm8994_priv { 69 struct wm8994_priv {
70 struct wm_hubs_data hubs; 70 struct wm_hubs_data hubs;
71 enum snd_soc_control_type control_type; 71 enum snd_soc_control_type control_type;
72 void *control_data; 72 void *control_data;
73 struct snd_soc_codec *codec; 73 struct snd_soc_codec *codec;
74 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
75 int sysclk[2]; 74 int sysclk[2];
76 int sysclk_rate[2]; 75 int sysclk_rate[2];
77 int mclk[2]; 76 int mclk[2];
78 int aifclk[2]; 77 int aifclk[2];
79 struct fll_config fll[2], fll_suspend[2]; 78 struct fll_config fll[2], fll_suspend[2];
80 79
81 int dac_rates[2]; 80 int dac_rates[2];
82 int lrclk_shared[2]; 81 int lrclk_shared[2];
83 82
83 int mbc_ena[3];
84
84 /* Platform dependant DRC configuration */ 85 /* Platform dependant DRC configuration */
85 const char **drc_texts; 86 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC]; 87 int drc_cfg[WM8994_NUM_DRC];
87 struct soc_enum drc_enum; 88 struct soc_enum drc_enum;
88 89
89 /* Platform dependant ReTune mobile configuration */ 90 /* Platform dependant ReTune mobile configuration */
90 int num_retune_mobile_texts; 91 int num_retune_mobile_texts;
91 const char **retune_mobile_texts; 92 const char **retune_mobile_texts;
92 int retune_mobile_cfg[WM8994_NUM_EQ]; 93 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum; 94 struct soc_enum retune_mobile_enum;
94 95
96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
95 struct wm8994_micdet micdet[2]; 101 struct wm8994_micdet micdet[2];
96 102
103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
107
97 int revision; 108 int revision;
98 struct wm8994_pdata *pdata; 109 struct wm8994_pdata *pdata;
110
111 unsigned int aif1clk_enable:1;
112 unsigned int aif2clk_enable:1;
99 }; 113 };
100 114
101 static const struct { 115 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
102 unsigned short readable; /* Mask of readable bits */
103 unsigned short writable; /* Mask of writable bits */
104 } access_masks[] = {
105 { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
106 { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
107 { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
108 { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
109 { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
110 { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
111 { 0x003F, 0x003F }, /* R6 - Power Management (6) */
112 { 0x0000, 0x0000 }, /* R7 */
113 { 0x0000, 0x0000 }, /* R8 */
114 { 0x0000, 0x0000 }, /* R9 */
115 { 0x0000, 0x0000 }, /* R10 */
116 { 0x0000, 0x0000 }, /* R11 */
117 { 0x0000, 0x0000 }, /* R12 */
118 { 0x0000, 0x0000 }, /* R13 */
119 { 0x0000, 0x0000 }, /* R14 */
120 { 0x0000, 0x0000 }, /* R15 */
121 { 0x0000, 0x0000 }, /* R16 */
122 { 0x0000, 0x0000 }, /* R17 */
123 { 0x0000, 0x0000 }, /* R18 */
124 { 0x0000, 0x0000 }, /* R19 */
125 { 0x0000, 0x0000 }, /* R20 */
126 { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
127 { 0x0000, 0x0000 }, /* R22 */
128 { 0x0000, 0x0000 }, /* R23 */
129 { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
130 { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
131 { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
132 { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
133 { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
134 { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
135 { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
136 { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
137 { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
138 { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
139 { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
140 { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
141 { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
142 { 0x003F, 0x003F }, /* R37 - ClassD */
143 { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
144 { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
145 { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
146 { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
147 { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
148 { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
149 { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
150 { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
151 { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
152 { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
153 { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
154 { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
155 { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
156 { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
157 { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
158 { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
159 { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
160 { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
161 { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
162 { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
163 { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
164 { 0x000F, 0x000F }, /* R59 - LDO 1 */
165 { 0x0007, 0x0007 }, /* R60 - LDO 2 */
166 { 0x0000, 0x0000 }, /* R61 */
167 { 0x0000, 0x0000 }, /* R62 */
168 { 0x0000, 0x0000 }, /* R63 */
169 { 0x0000, 0x0000 }, /* R64 */
170 { 0x0000, 0x0000 }, /* R65 */
171 { 0x0000, 0x0000 }, /* R66 */
172 { 0x0000, 0x0000 }, /* R67 */
173 { 0x0000, 0x0000 }, /* R68 */
174 { 0x0000, 0x0000 }, /* R69 */
175 { 0x0000, 0x0000 }, /* R70 */
176 { 0x0000, 0x0000 }, /* R71 */
177 { 0x0000, 0x0000 }, /* R72 */
178 { 0x0000, 0x0000 }, /* R73 */
179 { 0x0000, 0x0000 }, /* R74 */
180 { 0x0000, 0x0000 }, /* R75 */
181 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
182 { 0x0000, 0x0000 }, /* R77 */
183 { 0x0000, 0x0000 }, /* R78 */
184 { 0x0000, 0x0000 }, /* R79 */
185 { 0x0000, 0x0000 }, /* R80 */
186 { 0x0301, 0x0301 }, /* R81 - Class W (1) */
187 { 0x0000, 0x0000 }, /* R82 */
188 { 0x0000, 0x0000 }, /* R83 */
189 { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
190 { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
191 { 0x0000, 0x0000 }, /* R86 */
192 { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
193 { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
194 { 0x0000, 0x0000 }, /* R89 */
195 { 0x0000, 0x0000 }, /* R90 */
196 { 0x0000, 0x0000 }, /* R91 */
197 { 0x0000, 0x0000 }, /* R92 */
198 { 0x0000, 0x0000 }, /* R93 */
199 { 0x0000, 0x0000 }, /* R94 */
200 { 0x0000, 0x0000 }, /* R95 */
201 { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
202 { 0x0000, 0x0000 }, /* R97 */
203 { 0x0000, 0x0000 }, /* R98 */
204 { 0x0000, 0x0000 }, /* R99 */
205 { 0x0000, 0x0000 }, /* R100 */
206 { 0x0000, 0x0000 }, /* R101 */
207 { 0x0000, 0x0000 }, /* R102 */
208 { 0x0000, 0x0000 }, /* R103 */
209 { 0x0000, 0x0000 }, /* R104 */
210 { 0x0000, 0x0000 }, /* R105 */
211 { 0x0000, 0x0000 }, /* R106 */
212 { 0x0000, 0x0000 }, /* R107 */
213 { 0x0000, 0x0000 }, /* R108 */
214 { 0x0000, 0x0000 }, /* R109 */
215 { 0x0000, 0x0000 }, /* R110 */
216 { 0x0000, 0x0000 }, /* R111 */
217 { 0x0000, 0x0000 }, /* R112 */
218 { 0x0000, 0x0000 }, /* R113 */
219 { 0x0000, 0x0000 }, /* R114 */
220 { 0x0000, 0x0000 }, /* R115 */
221 { 0x0000, 0x0000 }, /* R116 */
222 { 0x0000, 0x0000 }, /* R117 */
223 { 0x0000, 0x0000 }, /* R118 */
224 { 0x0000, 0x0000 }, /* R119 */
225 { 0x0000, 0x0000 }, /* R120 */
226 { 0x0000, 0x0000 }, /* R121 */
227 { 0x0000, 0x0000 }, /* R122 */
228 { 0x0000, 0x0000 }, /* R123 */
229 { 0x0000, 0x0000 }, /* R124 */
230 { 0x0000, 0x0000 }, /* R125 */
231 { 0x0000, 0x0000 }, /* R126 */
232 { 0x0000, 0x0000 }, /* R127 */
233 { 0x0000, 0x0000 }, /* R128 */
234 { 0x0000, 0x0000 }, /* R129 */
235 { 0x0000, 0x0000 }, /* R130 */
236 { 0x0000, 0x0000 }, /* R131 */
237 { 0x0000, 0x0000 }, /* R132 */
238 { 0x0000, 0x0000 }, /* R133 */
239 { 0x0000, 0x0000 }, /* R134 */
240 { 0x0000, 0x0000 }, /* R135 */
241 { 0x0000, 0x0000 }, /* R136 */
242 { 0x0000, 0x0000 }, /* R137 */
243 { 0x0000, 0x0000 }, /* R138 */
244 { 0x0000, 0x0000 }, /* R139 */
245 { 0x0000, 0x0000 }, /* R140 */
246 { 0x0000, 0x0000 }, /* R141 */
247 { 0x0000, 0x0000 }, /* R142 */
248 { 0x0000, 0x0000 }, /* R143 */
249 { 0x0000, 0x0000 }, /* R144 */
250 { 0x0000, 0x0000 }, /* R145 */
251 { 0x0000, 0x0000 }, /* R146 */
252 { 0x0000, 0x0000 }, /* R147 */
253 { 0x0000, 0x0000 }, /* R148 */
254 { 0x0000, 0x0000 }, /* R149 */
255 { 0x0000, 0x0000 }, /* R150 */
256 { 0x0000, 0x0000 }, /* R151 */
257 { 0x0000, 0x0000 }, /* R152 */
258 { 0x0000, 0x0000 }, /* R153 */
259 { 0x0000, 0x0000 }, /* R154 */
260 { 0x0000, 0x0000 }, /* R155 */
261 { 0x0000, 0x0000 }, /* R156 */
262 { 0x0000, 0x0000 }, /* R157 */
263 { 0x0000, 0x0000 }, /* R158 */
264 { 0x0000, 0x0000 }, /* R159 */
265 { 0x0000, 0x0000 }, /* R160 */
266 { 0x0000, 0x0000 }, /* R161 */
267 { 0x0000, 0x0000 }, /* R162 */
268 { 0x0000, 0x0000 }, /* R163 */
269 { 0x0000, 0x0000 }, /* R164 */
270 { 0x0000, 0x0000 }, /* R165 */
271 { 0x0000, 0x0000 }, /* R166 */
272 { 0x0000, 0x0000 }, /* R167 */
273 { 0x0000, 0x0000 }, /* R168 */
274 { 0x0000, 0x0000 }, /* R169 */
275 { 0x0000, 0x0000 }, /* R170 */
276 { 0x0000, 0x0000 }, /* R171 */
277 { 0x0000, 0x0000 }, /* R172 */
278 { 0x0000, 0x0000 }, /* R173 */
279 { 0x0000, 0x0000 }, /* R174 */
280 { 0x0000, 0x0000 }, /* R175 */
281 { 0x0000, 0x0000 }, /* R176 */
282 { 0x0000, 0x0000 }, /* R177 */
283 { 0x0000, 0x0000 }, /* R178 */
284 { 0x0000, 0x0000 }, /* R179 */
285 { 0x0000, 0x0000 }, /* R180 */
286 { 0x0000, 0x0000 }, /* R181 */
287 { 0x0000, 0x0000 }, /* R182 */
288 { 0x0000, 0x0000 }, /* R183 */
289 { 0x0000, 0x0000 }, /* R184 */
290 { 0x0000, 0x0000 }, /* R185 */
291 { 0x0000, 0x0000 }, /* R186 */
292 { 0x0000, 0x0000 }, /* R187 */
293 { 0x0000, 0x0000 }, /* R188 */
294 { 0x0000, 0x0000 }, /* R189 */
295 { 0x0000, 0x0000 }, /* R190 */
296 { 0x0000, 0x0000 }, /* R191 */
297 { 0x0000, 0x0000 }, /* R192 */
298 { 0x0000, 0x0000 }, /* R193 */
299 { 0x0000, 0x0000 }, /* R194 */
300 { 0x0000, 0x0000 }, /* R195 */
301 { 0x0000, 0x0000 }, /* R196 */
302 { 0x0000, 0x0000 }, /* R197 */
303 { 0x0000, 0x0000 }, /* R198 */
304 { 0x0000, 0x0000 }, /* R199 */
305 { 0x0000, 0x0000 }, /* R200 */
306 { 0x0000, 0x0000 }, /* R201 */
307 { 0x0000, 0x0000 }, /* R202 */
308 { 0x0000, 0x0000 }, /* R203 */
309 { 0x0000, 0x0000 }, /* R204 */
310 { 0x0000, 0x0000 }, /* R205 */
311 { 0x0000, 0x0000 }, /* R206 */
312 { 0x0000, 0x0000 }, /* R207 */
313 { 0x0000, 0x0000 }, /* R208 */
314 { 0x0000, 0x0000 }, /* R209 */
315 { 0x0000, 0x0000 }, /* R210 */
316 { 0x0000, 0x0000 }, /* R211 */
317 { 0x0000, 0x0000 }, /* R212 */
318 { 0x0000, 0x0000 }, /* R213 */
319 { 0x0000, 0x0000 }, /* R214 */
320 { 0x0000, 0x0000 }, /* R215 */
321 { 0x0000, 0x0000 }, /* R216 */
322 { 0x0000, 0x0000 }, /* R217 */
323 { 0x0000, 0x0000 }, /* R218 */
324 { 0x0000, 0x0000 }, /* R219 */
325 { 0x0000, 0x0000 }, /* R220 */
326 { 0x0000, 0x0000 }, /* R221 */
327 { 0x0000, 0x0000 }, /* R222 */
328 { 0x0000, 0x0000 }, /* R223 */
329 { 0x0000, 0x0000 }, /* R224 */
330 { 0x0000, 0x0000 }, /* R225 */
331 { 0x0000, 0x0000 }, /* R226 */
332 { 0x0000, 0x0000 }, /* R227 */
333 { 0x0000, 0x0000 }, /* R228 */
334 { 0x0000, 0x0000 }, /* R229 */
335 { 0x0000, 0x0000 }, /* R230 */
336 { 0x0000, 0x0000 }, /* R231 */
337 { 0x0000, 0x0000 }, /* R232 */
338 { 0x0000, 0x0000 }, /* R233 */
339 { 0x0000, 0x0000 }, /* R234 */
340 { 0x0000, 0x0000 }, /* R235 */
341 { 0x0000, 0x0000 }, /* R236 */
342 { 0x0000, 0x0000 }, /* R237 */
343 { 0x0000, 0x0000 }, /* R238 */
344 { 0x0000, 0x0000 }, /* R239 */
345 { 0x0000, 0x0000 }, /* R240 */
346 { 0x0000, 0x0000 }, /* R241 */
347 { 0x0000, 0x0000 }, /* R242 */
348 { 0x0000, 0x0000 }, /* R243 */
349 { 0x0000, 0x0000 }, /* R244 */
350 { 0x0000, 0x0000 }, /* R245 */
351 { 0x0000, 0x0000 }, /* R246 */
352 { 0x0000, 0x0000 }, /* R247 */
353 { 0x0000, 0x0000 }, /* R248 */
354 { 0x0000, 0x0000 }, /* R249 */
355 { 0x0000, 0x0000 }, /* R250 */
356 { 0x0000, 0x0000 }, /* R251 */
357 { 0x0000, 0x0000 }, /* R252 */
358 { 0x0000, 0x0000 }, /* R253 */
359 { 0x0000, 0x0000 }, /* R254 */
360 { 0x0000, 0x0000 }, /* R255 */
361 { 0x000F, 0x0000 }, /* R256 - Chip Revision */
362 { 0x0074, 0x0074 }, /* R257 - Control Interface */
363 { 0x0000, 0x0000 }, /* R258 */
364 { 0x0000, 0x0000 }, /* R259 */
365 { 0x0000, 0x0000 }, /* R260 */
366 { 0x0000, 0x0000 }, /* R261 */
367 { 0x0000, 0x0000 }, /* R262 */
368 { 0x0000, 0x0000 }, /* R263 */
369 { 0x0000, 0x0000 }, /* R264 */
370 { 0x0000, 0x0000 }, /* R265 */
371 { 0x0000, 0x0000 }, /* R266 */
372 { 0x0000, 0x0000 }, /* R267 */
373 { 0x0000, 0x0000 }, /* R268 */
374 { 0x0000, 0x0000 }, /* R269 */
375 { 0x0000, 0x0000 }, /* R270 */
376 { 0x0000, 0x0000 }, /* R271 */
377 { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
378 { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
379 { 0x0000, 0x0000 }, /* R274 */
380 { 0x0000, 0x0000 }, /* R275 */
381 { 0x0000, 0x0000 }, /* R276 */
382 { 0x0000, 0x0000 }, /* R277 */
383 { 0x0000, 0x0000 }, /* R278 */
384 { 0x0000, 0x0000 }, /* R279 */
385 { 0x0000, 0x0000 }, /* R280 */
386 { 0x0000, 0x0000 }, /* R281 */
387 { 0x0000, 0x0000 }, /* R282 */
388 { 0x0000, 0x0000 }, /* R283 */
389 { 0x0000, 0x0000 }, /* R284 */
390 { 0x0000, 0x0000 }, /* R285 */
391 { 0x0000, 0x0000 }, /* R286 */
392 { 0x0000, 0x0000 }, /* R287 */
393 { 0x0000, 0x0000 }, /* R288 */
394 { 0x0000, 0x0000 }, /* R289 */
395 { 0x0000, 0x0000 }, /* R290 */
396 { 0x0000, 0x0000 }, /* R291 */
397 { 0x0000, 0x0000 }, /* R292 */
398 { 0x0000, 0x0000 }, /* R293 */
399 { 0x0000, 0x0000 }, /* R294 */
400 { 0x0000, 0x0000 }, /* R295 */
401 { 0x0000, 0x0000 }, /* R296 */
402 { 0x0000, 0x0000 }, /* R297 */
403 { 0x0000, 0x0000 }, /* R298 */
404 { 0x0000, 0x0000 }, /* R299 */
405 { 0x0000, 0x0000 }, /* R300 */
406 { 0x0000, 0x0000 }, /* R301 */
407 { 0x0000, 0x0000 }, /* R302 */
408 { 0x0000, 0x0000 }, /* R303 */
409 { 0x0000, 0x0000 }, /* R304 */
410 { 0x0000, 0x0000 }, /* R305 */
411 { 0x0000, 0x0000 }, /* R306 */
412 { 0x0000, 0x0000 }, /* R307 */
413 { 0x0000, 0x0000 }, /* R308 */
414 { 0x0000, 0x0000 }, /* R309 */
415 { 0x0000, 0x0000 }, /* R310 */
416 { 0x0000, 0x0000 }, /* R311 */
417 { 0x0000, 0x0000 }, /* R312 */
418 { 0x0000, 0x0000 }, /* R313 */
419 { 0x0000, 0x0000 }, /* R314 */
420 { 0x0000, 0x0000 }, /* R315 */
421 { 0x0000, 0x0000 }, /* R316 */
422 { 0x0000, 0x0000 }, /* R317 */
423 { 0x0000, 0x0000 }, /* R318 */
424 { 0x0000, 0x0000 }, /* R319 */
425 { 0x0000, 0x0000 }, /* R320 */
426 { 0x0000, 0x0000 }, /* R321 */
427 { 0x0000, 0x0000 }, /* R322 */
428 { 0x0000, 0x0000 }, /* R323 */
429 { 0x0000, 0x0000 }, /* R324 */
430 { 0x0000, 0x0000 }, /* R325 */
431 { 0x0000, 0x0000 }, /* R326 */
432 { 0x0000, 0x0000 }, /* R327 */
433 { 0x0000, 0x0000 }, /* R328 */
434 { 0x0000, 0x0000 }, /* R329 */
435 { 0x0000, 0x0000 }, /* R330 */
436 { 0x0000, 0x0000 }, /* R331 */
437 { 0x0000, 0x0000 }, /* R332 */
438 { 0x0000, 0x0000 }, /* R333 */
439 { 0x0000, 0x0000 }, /* R334 */
440 { 0x0000, 0x0000 }, /* R335 */
441 { 0x0000, 0x0000 }, /* R336 */
442 { 0x0000, 0x0000 }, /* R337 */
443 { 0x0000, 0x0000 }, /* R338 */
444 { 0x0000, 0x0000 }, /* R339 */
445 { 0x0000, 0x0000 }, /* R340 */
446 { 0x0000, 0x0000 }, /* R341 */
447 { 0x0000, 0x0000 }, /* R342 */
448 { 0x0000, 0x0000 }, /* R343 */
449 { 0x0000, 0x0000 }, /* R344 */
450 { 0x0000, 0x0000 }, /* R345 */
451 { 0x0000, 0x0000 }, /* R346 */
452 { 0x0000, 0x0000 }, /* R347 */
453 { 0x0000, 0x0000 }, /* R348 */
454 { 0x0000, 0x0000 }, /* R349 */
455 { 0x0000, 0x0000 }, /* R350 */
456 { 0x0000, 0x0000 }, /* R351 */
457 { 0x0000, 0x0000 }, /* R352 */
458 { 0x0000, 0x0000 }, /* R353 */
459 { 0x0000, 0x0000 }, /* R354 */
460 { 0x0000, 0x0000 }, /* R355 */
461 { 0x0000, 0x0000 }, /* R356 */
462 { 0x0000, 0x0000 }, /* R357 */
463 { 0x0000, 0x0000 }, /* R358 */
464 { 0x0000, 0x0000 }, /* R359 */
465 { 0x0000, 0x0000 }, /* R360 */
466 { 0x0000, 0x0000 }, /* R361 */
467 { 0x0000, 0x0000 }, /* R362 */
468 { 0x0000, 0x0000 }, /* R363 */
469 { 0x0000, 0x0000 }, /* R364 */
470 { 0x0000, 0x0000 }, /* R365 */
471 { 0x0000, 0x0000 }, /* R366 */
472 { 0x0000, 0x0000 }, /* R367 */
473 { 0x0000, 0x0000 }, /* R368 */
474 { 0x0000, 0x0000 }, /* R369 */
475 { 0x0000, 0x0000 }, /* R370 */
476 { 0x0000, 0x0000 }, /* R371 */
477 { 0x0000, 0x0000 }, /* R372 */
478 { 0x0000, 0x0000 }, /* R373 */
479 { 0x0000, 0x0000 }, /* R374 */
480 { 0x0000, 0x0000 }, /* R375 */
481 { 0x0000, 0x0000 }, /* R376 */
482 { 0x0000, 0x0000 }, /* R377 */
483 { 0x0000, 0x0000 }, /* R378 */
484 { 0x0000, 0x0000 }, /* R379 */
485 { 0x0000, 0x0000 }, /* R380 */
486 { 0x0000, 0x0000 }, /* R381 */
487 { 0x0000, 0x0000 }, /* R382 */
488 { 0x0000, 0x0000 }, /* R383 */
489 { 0x0000, 0x0000 }, /* R384 */
490 { 0x0000, 0x0000 }, /* R385 */
491 { 0x0000, 0x0000 }, /* R386 */
492 { 0x0000, 0x0000 }, /* R387 */
493 { 0x0000, 0x0000 }, /* R388 */
494 { 0x0000, 0x0000 }, /* R389 */
495 { 0x0000, 0x0000 }, /* R390 */
496 { 0x0000, 0x0000 }, /* R391 */
497 { 0x0000, 0x0000 }, /* R392 */
498 { 0x0000, 0x0000 }, /* R393 */
499 { 0x0000, 0x0000 }, /* R394 */
500 { 0x0000, 0x0000 }, /* R395 */
501 { 0x0000, 0x0000 }, /* R396 */
502 { 0x0000, 0x0000 }, /* R397 */
503 { 0x0000, 0x0000 }, /* R398 */
504 { 0x0000, 0x0000 }, /* R399 */
505 { 0x0000, 0x0000 }, /* R400 */
506 { 0x0000, 0x0000 }, /* R401 */
507 { 0x0000, 0x0000 }, /* R402 */
508 { 0x0000, 0x0000 }, /* R403 */
509 { 0x0000, 0x0000 }, /* R404 */
510 { 0x0000, 0x0000 }, /* R405 */
511 { 0x0000, 0x0000 }, /* R406 */
512 { 0x0000, 0x0000 }, /* R407 */
513 { 0x0000, 0x0000 }, /* R408 */
514 { 0x0000, 0x0000 }, /* R409 */
515 { 0x0000, 0x0000 }, /* R410 */
516 { 0x0000, 0x0000 }, /* R411 */
517 { 0x0000, 0x0000 }, /* R412 */
518 { 0x0000, 0x0000 }, /* R413 */
519 { 0x0000, 0x0000 }, /* R414 */
520 { 0x0000, 0x0000 }, /* R415 */
521 { 0x0000, 0x0000 }, /* R416 */
522 { 0x0000, 0x0000 }, /* R417 */
523 { 0x0000, 0x0000 }, /* R418 */
524 { 0x0000, 0x0000 }, /* R419 */
525 { 0x0000, 0x0000 }, /* R420 */
526 { 0x0000, 0x0000 }, /* R421 */
527 { 0x0000, 0x0000 }, /* R422 */
528 { 0x0000, 0x0000 }, /* R423 */
529 { 0x0000, 0x0000 }, /* R424 */
530 { 0x0000, 0x0000 }, /* R425 */
531 { 0x0000, 0x0000 }, /* R426 */
532 { 0x0000, 0x0000 }, /* R427 */
533 { 0x0000, 0x0000 }, /* R428 */
534 { 0x0000, 0x0000 }, /* R429 */
535 { 0x0000, 0x0000 }, /* R430 */
536 { 0x0000, 0x0000 }, /* R431 */
537 { 0x0000, 0x0000 }, /* R432 */
538 { 0x0000, 0x0000 }, /* R433 */
539 { 0x0000, 0x0000 }, /* R434 */
540 { 0x0000, 0x0000 }, /* R435 */
541 { 0x0000, 0x0000 }, /* R436 */
542 { 0x0000, 0x0000 }, /* R437 */
543 { 0x0000, 0x0000 }, /* R438 */
544 { 0x0000, 0x0000 }, /* R439 */
545 { 0x0000, 0x0000 }, /* R440 */
546 { 0x0000, 0x0000 }, /* R441 */
547 { 0x0000, 0x0000 }, /* R442 */
548 { 0x0000, 0x0000 }, /* R443 */
549 { 0x0000, 0x0000 }, /* R444 */
550 { 0x0000, 0x0000 }, /* R445 */
551 { 0x0000, 0x0000 }, /* R446 */
552 { 0x0000, 0x0000 }, /* R447 */
553 { 0x0000, 0x0000 }, /* R448 */
554 { 0x0000, 0x0000 }, /* R449 */
555 { 0x0000, 0x0000 }, /* R450 */
556 { 0x0000, 0x0000 }, /* R451 */
557 { 0x0000, 0x0000 }, /* R452 */
558 { 0x0000, 0x0000 }, /* R453 */
559 { 0x0000, 0x0000 }, /* R454 */
560 { 0x0000, 0x0000 }, /* R455 */
561 { 0x0000, 0x0000 }, /* R456 */
562 { 0x0000, 0x0000 }, /* R457 */
563 { 0x0000, 0x0000 }, /* R458 */
564 { 0x0000, 0x0000 }, /* R459 */
565 { 0x0000, 0x0000 }, /* R460 */
566 { 0x0000, 0x0000 }, /* R461 */
567 { 0x0000, 0x0000 }, /* R462 */
568 { 0x0000, 0x0000 }, /* R463 */
569 { 0x0000, 0x0000 }, /* R464 */
570 { 0x0000, 0x0000 }, /* R465 */
571 { 0x0000, 0x0000 }, /* R466 */
572 { 0x0000, 0x0000 }, /* R467 */
573 { 0x0000, 0x0000 }, /* R468 */
574 { 0x0000, 0x0000 }, /* R469 */
575 { 0x0000, 0x0000 }, /* R470 */
576 { 0x0000, 0x0000 }, /* R471 */
577 { 0x0000, 0x0000 }, /* R472 */
578 { 0x0000, 0x0000 }, /* R473 */
579 { 0x0000, 0x0000 }, /* R474 */
580 { 0x0000, 0x0000 }, /* R475 */
581 { 0x0000, 0x0000 }, /* R476 */
582 { 0x0000, 0x0000 }, /* R477 */
583 { 0x0000, 0x0000 }, /* R478 */
584 { 0x0000, 0x0000 }, /* R479 */
585 { 0x0000, 0x0000 }, /* R480 */
586 { 0x0000, 0x0000 }, /* R481 */
587 { 0x0000, 0x0000 }, /* R482 */
588 { 0x0000, 0x0000 }, /* R483 */
589 { 0x0000, 0x0000 }, /* R484 */
590 { 0x0000, 0x0000 }, /* R485 */
591 { 0x0000, 0x0000 }, /* R486 */
592 { 0x0000, 0x0000 }, /* R487 */
593 { 0x0000, 0x0000 }, /* R488 */
594 { 0x0000, 0x0000 }, /* R489 */
595 { 0x0000, 0x0000 }, /* R490 */
596 { 0x0000, 0x0000 }, /* R491 */
597 { 0x0000, 0x0000 }, /* R492 */
598 { 0x0000, 0x0000 }, /* R493 */
599 { 0x0000, 0x0000 }, /* R494 */
600 { 0x0000, 0x0000 }, /* R495 */
601 { 0x0000, 0x0000 }, /* R496 */
602 { 0x0000, 0x0000 }, /* R497 */
603 { 0x0000, 0x0000 }, /* R498 */
604 { 0x0000, 0x0000 }, /* R499 */
605 { 0x0000, 0x0000 }, /* R500 */
606 { 0x0000, 0x0000 }, /* R501 */
607 { 0x0000, 0x0000 }, /* R502 */
608 { 0x0000, 0x0000 }, /* R503 */
609 { 0x0000, 0x0000 }, /* R504 */
610 { 0x0000, 0x0000 }, /* R505 */
611 { 0x0000, 0x0000 }, /* R506 */
612 { 0x0000, 0x0000 }, /* R507 */
613 { 0x0000, 0x0000 }, /* R508 */
614 { 0x0000, 0x0000 }, /* R509 */
615 { 0x0000, 0x0000 }, /* R510 */
616 { 0x0000, 0x0000 }, /* R511 */
617 { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
618 { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
619 { 0x0000, 0x0000 }, /* R514 */
620 { 0x0000, 0x0000 }, /* R515 */
621 { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
622 { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
623 { 0x0000, 0x0000 }, /* R518 */
624 { 0x0000, 0x0000 }, /* R519 */
625 { 0x001F, 0x001F }, /* R520 - Clocking (1) */
626 { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
627 { 0x0000, 0x0000 }, /* R522 */
628 { 0x0000, 0x0000 }, /* R523 */
629 { 0x0000, 0x0000 }, /* R524 */
630 { 0x0000, 0x0000 }, /* R525 */
631 { 0x0000, 0x0000 }, /* R526 */
632 { 0x0000, 0x0000 }, /* R527 */
633 { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
634 { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
635 { 0x000F, 0x0000 }, /* R530 - Rate Status */
636 { 0x0000, 0x0000 }, /* R531 */
637 { 0x0000, 0x0000 }, /* R532 */
638 { 0x0000, 0x0000 }, /* R533 */
639 { 0x0000, 0x0000 }, /* R534 */
640 { 0x0000, 0x0000 }, /* R535 */
641 { 0x0000, 0x0000 }, /* R536 */
642 { 0x0000, 0x0000 }, /* R537 */
643 { 0x0000, 0x0000 }, /* R538 */
644 { 0x0000, 0x0000 }, /* R539 */
645 { 0x0000, 0x0000 }, /* R540 */
646 { 0x0000, 0x0000 }, /* R541 */
647 { 0x0000, 0x0000 }, /* R542 */
648 { 0x0000, 0x0000 }, /* R543 */
649 { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
650 { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
651 { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
652 { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
653 { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
654 { 0x0000, 0x0000 }, /* R549 */
655 { 0x0000, 0x0000 }, /* R550 */
656 { 0x0000, 0x0000 }, /* R551 */
657 { 0x0000, 0x0000 }, /* R552 */
658 { 0x0000, 0x0000 }, /* R553 */
659 { 0x0000, 0x0000 }, /* R554 */
660 { 0x0000, 0x0000 }, /* R555 */
661 { 0x0000, 0x0000 }, /* R556 */
662 { 0x0000, 0x0000 }, /* R557 */
663 { 0x0000, 0x0000 }, /* R558 */
664 { 0x0000, 0x0000 }, /* R559 */
665 { 0x0000, 0x0000 }, /* R560 */
666 { 0x0000, 0x0000 }, /* R561 */
667 { 0x0000, 0x0000 }, /* R562 */
668 { 0x0000, 0x0000 }, /* R563 */
669 { 0x0000, 0x0000 }, /* R564 */
670 { 0x0000, 0x0000 }, /* R565 */
671 { 0x0000, 0x0000 }, /* R566 */
672 { 0x0000, 0x0000 }, /* R567 */
673 { 0x0000, 0x0000 }, /* R568 */
674 { 0x0000, 0x0000 }, /* R569 */
675 { 0x0000, 0x0000 }, /* R570 */
676 { 0x0000, 0x0000 }, /* R571 */
677 { 0x0000, 0x0000 }, /* R572 */
678 { 0x0000, 0x0000 }, /* R573 */
679 { 0x0000, 0x0000 }, /* R574 */
680 { 0x0000, 0x0000 }, /* R575 */
681 { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
682 { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
683 { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
684 { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
685 { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
686 { 0x0000, 0x0000 }, /* R581 */
687 { 0x0000, 0x0000 }, /* R582 */
688 { 0x0000, 0x0000 }, /* R583 */
689 { 0x0000, 0x0000 }, /* R584 */
690 { 0x0000, 0x0000 }, /* R585 */
691 { 0x0000, 0x0000 }, /* R586 */
692 { 0x0000, 0x0000 }, /* R587 */
693 { 0x0000, 0x0000 }, /* R588 */
694 { 0x0000, 0x0000 }, /* R589 */
695 { 0x0000, 0x0000 }, /* R590 */
696 { 0x0000, 0x0000 }, /* R591 */
697 { 0x0000, 0x0000 }, /* R592 */
698 { 0x0000, 0x0000 }, /* R593 */
699 { 0x0000, 0x0000 }, /* R594 */
700 { 0x0000, 0x0000 }, /* R595 */
701 { 0x0000, 0x0000 }, /* R596 */
702 { 0x0000, 0x0000 }, /* R597 */
703 { 0x0000, 0x0000 }, /* R598 */
704 { 0x0000, 0x0000 }, /* R599 */
705 { 0x0000, 0x0000 }, /* R600 */
706 { 0x0000, 0x0000 }, /* R601 */
707 { 0x0000, 0x0000 }, /* R602 */
708 { 0x0000, 0x0000 }, /* R603 */
709 { 0x0000, 0x0000 }, /* R604 */
710 { 0x0000, 0x0000 }, /* R605 */
711 { 0x0000, 0x0000 }, /* R606 */
712 { 0x0000, 0x0000 }, /* R607 */
713 { 0x0000, 0x0000 }, /* R608 */
714 { 0x0000, 0x0000 }, /* R609 */
715 { 0x0000, 0x0000 }, /* R610 */
716 { 0x0000, 0x0000 }, /* R611 */
717 { 0x0000, 0x0000 }, /* R612 */
718 { 0x0000, 0x0000 }, /* R613 */
719 { 0x0000, 0x0000 }, /* R614 */
720 { 0x0000, 0x0000 }, /* R615 */
721 { 0x0000, 0x0000 }, /* R616 */
722 { 0x0000, 0x0000 }, /* R617 */
723 { 0x0000, 0x0000 }, /* R618 */
724 { 0x0000, 0x0000 }, /* R619 */
725 { 0x0000, 0x0000 }, /* R620 */
726 { 0x0000, 0x0000 }, /* R621 */
727 { 0x0000, 0x0000 }, /* R622 */
728 { 0x0000, 0x0000 }, /* R623 */
729 { 0x0000, 0x0000 }, /* R624 */
730 { 0x0000, 0x0000 }, /* R625 */
731 { 0x0000, 0x0000 }, /* R626 */
732 { 0x0000, 0x0000 }, /* R627 */
733 { 0x0000, 0x0000 }, /* R628 */
734 { 0x0000, 0x0000 }, /* R629 */
735 { 0x0000, 0x0000 }, /* R630 */
736 { 0x0000, 0x0000 }, /* R631 */
737 { 0x0000, 0x0000 }, /* R632 */
738 { 0x0000, 0x0000 }, /* R633 */
739 { 0x0000, 0x0000 }, /* R634 */
740 { 0x0000, 0x0000 }, /* R635 */
741 { 0x0000, 0x0000 }, /* R636 */
742 { 0x0000, 0x0000 }, /* R637 */
743 { 0x0000, 0x0000 }, /* R638 */
744 { 0x0000, 0x0000 }, /* R639 */
745 { 0x0000, 0x0000 }, /* R640 */
746 { 0x0000, 0x0000 }, /* R641 */
747 { 0x0000, 0x0000 }, /* R642 */
748 { 0x0000, 0x0000 }, /* R643 */
749 { 0x0000, 0x0000 }, /* R644 */
750 { 0x0000, 0x0000 }, /* R645 */
751 { 0x0000, 0x0000 }, /* R646 */
752 { 0x0000, 0x0000 }, /* R647 */
753 { 0x0000, 0x0000 }, /* R648 */
754 { 0x0000, 0x0000 }, /* R649 */
755 { 0x0000, 0x0000 }, /* R650 */
756 { 0x0000, 0x0000 }, /* R651 */
757 { 0x0000, 0x0000 }, /* R652 */
758 { 0x0000, 0x0000 }, /* R653 */
759 { 0x0000, 0x0000 }, /* R654 */
760 { 0x0000, 0x0000 }, /* R655 */
761 { 0x0000, 0x0000 }, /* R656 */
762 { 0x0000, 0x0000 }, /* R657 */
763 { 0x0000, 0x0000 }, /* R658 */
764 { 0x0000, 0x0000 }, /* R659 */
765 { 0x0000, 0x0000 }, /* R660 */
766 { 0x0000, 0x0000 }, /* R661 */
767 { 0x0000, 0x0000 }, /* R662 */
768 { 0x0000, 0x0000 }, /* R663 */
769 { 0x0000, 0x0000 }, /* R664 */
770 { 0x0000, 0x0000 }, /* R665 */
771 { 0x0000, 0x0000 }, /* R666 */
772 { 0x0000, 0x0000 }, /* R667 */
773 { 0x0000, 0x0000 }, /* R668 */
774 { 0x0000, 0x0000 }, /* R669 */
775 { 0x0000, 0x0000 }, /* R670 */
776 { 0x0000, 0x0000 }, /* R671 */
777 { 0x0000, 0x0000 }, /* R672 */
778 { 0x0000, 0x0000 }, /* R673 */
779 { 0x0000, 0x0000 }, /* R674 */
780 { 0x0000, 0x0000 }, /* R675 */
781 { 0x0000, 0x0000 }, /* R676 */
782 { 0x0000, 0x0000 }, /* R677 */
783 { 0x0000, 0x0000 }, /* R678 */
784 { 0x0000, 0x0000 }, /* R679 */
785 { 0x0000, 0x0000 }, /* R680 */
786 { 0x0000, 0x0000 }, /* R681 */
787 { 0x0000, 0x0000 }, /* R682 */
788 { 0x0000, 0x0000 }, /* R683 */
789 { 0x0000, 0x0000 }, /* R684 */
790 { 0x0000, 0x0000 }, /* R685 */
791 { 0x0000, 0x0000 }, /* R686 */
792 { 0x0000, 0x0000 }, /* R687 */
793 { 0x0000, 0x0000 }, /* R688 */
794 { 0x0000, 0x0000 }, /* R689 */
795 { 0x0000, 0x0000 }, /* R690 */
796 { 0x0000, 0x0000 }, /* R691 */
797 { 0x0000, 0x0000 }, /* R692 */
798 { 0x0000, 0x0000 }, /* R693 */
799 { 0x0000, 0x0000 }, /* R694 */
800 { 0x0000, 0x0000 }, /* R695 */
801 { 0x0000, 0x0000 }, /* R696 */
802 { 0x0000, 0x0000 }, /* R697 */
803 { 0x0000, 0x0000 }, /* R698 */
804 { 0x0000, 0x0000 }, /* R699 */
805 { 0x0000, 0x0000 }, /* R700 */
806 { 0x0000, 0x0000 }, /* R701 */
807 { 0x0000, 0x0000 }, /* R702 */
808 { 0x0000, 0x0000 }, /* R703 */
809 { 0x0000, 0x0000 }, /* R704 */
810 { 0x0000, 0x0000 }, /* R705 */
811 { 0x0000, 0x0000 }, /* R706 */
812 { 0x0000, 0x0000 }, /* R707 */
813 { 0x0000, 0x0000 }, /* R708 */
814 { 0x0000, 0x0000 }, /* R709 */
815 { 0x0000, 0x0000 }, /* R710 */
816 { 0x0000, 0x0000 }, /* R711 */
817 { 0x0000, 0x0000 }, /* R712 */
818 { 0x0000, 0x0000 }, /* R713 */
819 { 0x0000, 0x0000 }, /* R714 */
820 { 0x0000, 0x0000 }, /* R715 */
821 { 0x0000, 0x0000 }, /* R716 */
822 { 0x0000, 0x0000 }, /* R717 */
823 { 0x0000, 0x0000 }, /* R718 */
824 { 0x0000, 0x0000 }, /* R719 */
825 { 0x0000, 0x0000 }, /* R720 */
826 { 0x0000, 0x0000 }, /* R721 */
827 { 0x0000, 0x0000 }, /* R722 */
828 { 0x0000, 0x0000 }, /* R723 */
829 { 0x0000, 0x0000 }, /* R724 */
830 { 0x0000, 0x0000 }, /* R725 */
831 { 0x0000, 0x0000 }, /* R726 */
832 { 0x0000, 0x0000 }, /* R727 */
833 { 0x0000, 0x0000 }, /* R728 */
834 { 0x0000, 0x0000 }, /* R729 */
835 { 0x0000, 0x0000 }, /* R730 */
836 { 0x0000, 0x0000 }, /* R731 */
837 { 0x0000, 0x0000 }, /* R732 */
838 { 0x0000, 0x0000 }, /* R733 */
839 { 0x0000, 0x0000 }, /* R734 */
840 { 0x0000, 0x0000 }, /* R735 */
841 { 0x0000, 0x0000 }, /* R736 */
842 { 0x0000, 0x0000 }, /* R737 */
843 { 0x0000, 0x0000 }, /* R738 */
844 { 0x0000, 0x0000 }, /* R739 */
845 { 0x0000, 0x0000 }, /* R740 */
846 { 0x0000, 0x0000 }, /* R741 */
847 { 0x0000, 0x0000 }, /* R742 */
848 { 0x0000, 0x0000 }, /* R743 */
849 { 0x0000, 0x0000 }, /* R744 */
850 { 0x0000, 0x0000 }, /* R745 */
851 { 0x0000, 0x0000 }, /* R746 */
852 { 0x0000, 0x0000 }, /* R747 */
853 { 0x0000, 0x0000 }, /* R748 */
854 { 0x0000, 0x0000 }, /* R749 */
855 { 0x0000, 0x0000 }, /* R750 */
856 { 0x0000, 0x0000 }, /* R751 */
857 { 0x0000, 0x0000 }, /* R752 */
858 { 0x0000, 0x0000 }, /* R753 */
859 { 0x0000, 0x0000 }, /* R754 */
860 { 0x0000, 0x0000 }, /* R755 */
861 { 0x0000, 0x0000 }, /* R756 */
862 { 0x0000, 0x0000 }, /* R757 */
863 { 0x0000, 0x0000 }, /* R758 */
864 { 0x0000, 0x0000 }, /* R759 */
865 { 0x0000, 0x0000 }, /* R760 */
866 { 0x0000, 0x0000 }, /* R761 */
867 { 0x0000, 0x0000 }, /* R762 */
868 { 0x0000, 0x0000 }, /* R763 */
869 { 0x0000, 0x0000 }, /* R764 */
870 { 0x0000, 0x0000 }, /* R765 */
871 { 0x0000, 0x0000 }, /* R766 */
872 { 0x0000, 0x0000 }, /* R767 */
873 { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
874 { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
875 { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
876 { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
877 { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
878 { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
879 { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
880 { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
881 { 0x0000, 0x0000 }, /* R776 */
882 { 0x0000, 0x0000 }, /* R777 */
883 { 0x0000, 0x0000 }, /* R778 */
884 { 0x0000, 0x0000 }, /* R779 */
885 { 0x0000, 0x0000 }, /* R780 */
886 { 0x0000, 0x0000 }, /* R781 */
887 { 0x0000, 0x0000 }, /* R782 */
888 { 0x0000, 0x0000 }, /* R783 */
889 { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
890 { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
891 { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
892 { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
893 { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
894 { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
895 { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
896 { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
897 { 0x0000, 0x0000 }, /* R792 */
898 { 0x0000, 0x0000 }, /* R793 */
899 { 0x0000, 0x0000 }, /* R794 */
900 { 0x0000, 0x0000 }, /* R795 */
901 { 0x0000, 0x0000 }, /* R796 */
902 { 0x0000, 0x0000 }, /* R797 */
903 { 0x0000, 0x0000 }, /* R798 */
904 { 0x0000, 0x0000 }, /* R799 */
905 { 0x0000, 0x0000 }, /* R800 */
906 { 0x0000, 0x0000 }, /* R801 */
907 { 0x0000, 0x0000 }, /* R802 */
908 { 0x0000, 0x0000 }, /* R803 */
909 { 0x0000, 0x0000 }, /* R804 */
910 { 0x0000, 0x0000 }, /* R805 */
911 { 0x0000, 0x0000 }, /* R806 */
912 { 0x0000, 0x0000 }, /* R807 */
913 { 0x0000, 0x0000 }, /* R808 */
914 { 0x0000, 0x0000 }, /* R809 */
915 { 0x0000, 0x0000 }, /* R810 */
916 { 0x0000, 0x0000 }, /* R811 */
917 { 0x0000, 0x0000 }, /* R812 */
918 { 0x0000, 0x0000 }, /* R813 */
919 { 0x0000, 0x0000 }, /* R814 */
920 { 0x0000, 0x0000 }, /* R815 */
921 { 0x0000, 0x0000 }, /* R816 */
922 { 0x0000, 0x0000 }, /* R817 */
923 { 0x0000, 0x0000 }, /* R818 */
924 { 0x0000, 0x0000 }, /* R819 */
925 { 0x0000, 0x0000 }, /* R820 */
926 { 0x0000, 0x0000 }, /* R821 */
927 { 0x0000, 0x0000 }, /* R822 */
928 { 0x0000, 0x0000 }, /* R823 */
929 { 0x0000, 0x0000 }, /* R824 */
930 { 0x0000, 0x0000 }, /* R825 */
931 { 0x0000, 0x0000 }, /* R826 */
932 { 0x0000, 0x0000 }, /* R827 */
933 { 0x0000, 0x0000 }, /* R828 */
934 { 0x0000, 0x0000 }, /* R829 */
935 { 0x0000, 0x0000 }, /* R830 */
936 { 0x0000, 0x0000 }, /* R831 */
937 { 0x0000, 0x0000 }, /* R832 */
938 { 0x0000, 0x0000 }, /* R833 */
939 { 0x0000, 0x0000 }, /* R834 */
940 { 0x0000, 0x0000 }, /* R835 */
941 { 0x0000, 0x0000 }, /* R836 */
942 { 0x0000, 0x0000 }, /* R837 */
943 { 0x0000, 0x0000 }, /* R838 */
944 { 0x0000, 0x0000 }, /* R839 */
945 { 0x0000, 0x0000 }, /* R840 */
946 { 0x0000, 0x0000 }, /* R841 */
947 { 0x0000, 0x0000 }, /* R842 */
948 { 0x0000, 0x0000 }, /* R843 */
949 { 0x0000, 0x0000 }, /* R844 */
950 { 0x0000, 0x0000 }, /* R845 */
951 { 0x0000, 0x0000 }, /* R846 */
952 { 0x0000, 0x0000 }, /* R847 */
953 { 0x0000, 0x0000 }, /* R848 */
954 { 0x0000, 0x0000 }, /* R849 */
955 { 0x0000, 0x0000 }, /* R850 */
956 { 0x0000, 0x0000 }, /* R851 */
957 { 0x0000, 0x0000 }, /* R852 */
958 { 0x0000, 0x0000 }, /* R853 */
959 { 0x0000, 0x0000 }, /* R854 */
960 { 0x0000, 0x0000 }, /* R855 */
961 { 0x0000, 0x0000 }, /* R856 */
962 { 0x0000, 0x0000 }, /* R857 */
963 { 0x0000, 0x0000 }, /* R858 */
964 { 0x0000, 0x0000 }, /* R859 */
965 { 0x0000, 0x0000 }, /* R860 */
966 { 0x0000, 0x0000 }, /* R861 */
967 { 0x0000, 0x0000 }, /* R862 */
968 { 0x0000, 0x0000 }, /* R863 */
969 { 0x0000, 0x0000 }, /* R864 */
970 { 0x0000, 0x0000 }, /* R865 */
971 { 0x0000, 0x0000 }, /* R866 */
972 { 0x0000, 0x0000 }, /* R867 */
973 { 0x0000, 0x0000 }, /* R868 */
974 { 0x0000, 0x0000 }, /* R869 */
975 { 0x0000, 0x0000 }, /* R870 */
976 { 0x0000, 0x0000 }, /* R871 */
977 { 0x0000, 0x0000 }, /* R872 */
978 { 0x0000, 0x0000 }, /* R873 */
979 { 0x0000, 0x0000 }, /* R874 */
980 { 0x0000, 0x0000 }, /* R875 */
981 { 0x0000, 0x0000 }, /* R876 */
982 { 0x0000, 0x0000 }, /* R877 */
983 { 0x0000, 0x0000 }, /* R878 */
984 { 0x0000, 0x0000 }, /* R879 */
985 { 0x0000, 0x0000 }, /* R880 */
986 { 0x0000, 0x0000 }, /* R881 */
987 { 0x0000, 0x0000 }, /* R882 */
988 { 0x0000, 0x0000 }, /* R883 */
989 { 0x0000, 0x0000 }, /* R884 */
990 { 0x0000, 0x0000 }, /* R885 */
991 { 0x0000, 0x0000 }, /* R886 */
992 { 0x0000, 0x0000 }, /* R887 */
993 { 0x0000, 0x0000 }, /* R888 */
994 { 0x0000, 0x0000 }, /* R889 */
995 { 0x0000, 0x0000 }, /* R890 */
996 { 0x0000, 0x0000 }, /* R891 */
997 { 0x0000, 0x0000 }, /* R892 */
998 { 0x0000, 0x0000 }, /* R893 */
999 { 0x0000, 0x0000 }, /* R894 */
1000 { 0x0000, 0x0000 }, /* R895 */
1001 { 0x0000, 0x0000 }, /* R896 */
1002 { 0x0000, 0x0000 }, /* R897 */
1003 { 0x0000, 0x0000 }, /* R898 */
1004 { 0x0000, 0x0000 }, /* R899 */
1005 { 0x0000, 0x0000 }, /* R900 */
1006 { 0x0000, 0x0000 }, /* R901 */
1007 { 0x0000, 0x0000 }, /* R902 */
1008 { 0x0000, 0x0000 }, /* R903 */
1009 { 0x0000, 0x0000 }, /* R904 */
1010 { 0x0000, 0x0000 }, /* R905 */
1011 { 0x0000, 0x0000 }, /* R906 */
1012 { 0x0000, 0x0000 }, /* R907 */
1013 { 0x0000, 0x0000 }, /* R908 */
1014 { 0x0000, 0x0000 }, /* R909 */
1015 { 0x0000, 0x0000 }, /* R910 */
1016 { 0x0000, 0x0000 }, /* R911 */
1017 { 0x0000, 0x0000 }, /* R912 */
1018 { 0x0000, 0x0000 }, /* R913 */
1019 { 0x0000, 0x0000 }, /* R914 */
1020 { 0x0000, 0x0000 }, /* R915 */
1021 { 0x0000, 0x0000 }, /* R916 */
1022 { 0x0000, 0x0000 }, /* R917 */
1023 { 0x0000, 0x0000 }, /* R918 */
1024 { 0x0000, 0x0000 }, /* R919 */
1025 { 0x0000, 0x0000 }, /* R920 */
1026 { 0x0000, 0x0000 }, /* R921 */
1027 { 0x0000, 0x0000 }, /* R922 */
1028 { 0x0000, 0x0000 }, /* R923 */
1029 { 0x0000, 0x0000 }, /* R924 */
1030 { 0x0000, 0x0000 }, /* R925 */
1031 { 0x0000, 0x0000 }, /* R926 */
1032 { 0x0000, 0x0000 }, /* R927 */
1033 { 0x0000, 0x0000 }, /* R928 */
1034 { 0x0000, 0x0000 }, /* R929 */
1035 { 0x0000, 0x0000 }, /* R930 */
1036 { 0x0000, 0x0000 }, /* R931 */
1037 { 0x0000, 0x0000 }, /* R932 */
1038 { 0x0000, 0x0000 }, /* R933 */
1039 { 0x0000, 0x0000 }, /* R934 */
1040 { 0x0000, 0x0000 }, /* R935 */
1041 { 0x0000, 0x0000 }, /* R936 */
1042 { 0x0000, 0x0000 }, /* R937 */
1043 { 0x0000, 0x0000 }, /* R938 */
1044 { 0x0000, 0x0000 }, /* R939 */
1045 { 0x0000, 0x0000 }, /* R940 */
1046 { 0x0000, 0x0000 }, /* R941 */
1047 { 0x0000, 0x0000 }, /* R942 */
1048 { 0x0000, 0x0000 }, /* R943 */
1049 { 0x0000, 0x0000 }, /* R944 */
1050 { 0x0000, 0x0000 }, /* R945 */
1051 { 0x0000, 0x0000 }, /* R946 */
1052 { 0x0000, 0x0000 }, /* R947 */
1053 { 0x0000, 0x0000 }, /* R948 */
1054 { 0x0000, 0x0000 }, /* R949 */
1055 { 0x0000, 0x0000 }, /* R950 */
1056 { 0x0000, 0x0000 }, /* R951 */
1057 { 0x0000, 0x0000 }, /* R952 */
1058 { 0x0000, 0x0000 }, /* R953 */
1059 { 0x0000, 0x0000 }, /* R954 */
1060 { 0x0000, 0x0000 }, /* R955 */
1061 { 0x0000, 0x0000 }, /* R956 */
1062 { 0x0000, 0x0000 }, /* R957 */
1063 { 0x0000, 0x0000 }, /* R958 */
1064 { 0x0000, 0x0000 }, /* R959 */
1065 { 0x0000, 0x0000 }, /* R960 */
1066 { 0x0000, 0x0000 }, /* R961 */
1067 { 0x0000, 0x0000 }, /* R962 */
1068 { 0x0000, 0x0000 }, /* R963 */
1069 { 0x0000, 0x0000 }, /* R964 */
1070 { 0x0000, 0x0000 }, /* R965 */
1071 { 0x0000, 0x0000 }, /* R966 */
1072 { 0x0000, 0x0000 }, /* R967 */
1073 { 0x0000, 0x0000 }, /* R968 */
1074 { 0x0000, 0x0000 }, /* R969 */
1075 { 0x0000, 0x0000 }, /* R970 */
1076 { 0x0000, 0x0000 }, /* R971 */
1077 { 0x0000, 0x0000 }, /* R972 */
1078 { 0x0000, 0x0000 }, /* R973 */
1079 { 0x0000, 0x0000 }, /* R974 */
1080 { 0x0000, 0x0000 }, /* R975 */
1081 { 0x0000, 0x0000 }, /* R976 */
1082 { 0x0000, 0x0000 }, /* R977 */
1083 { 0x0000, 0x0000 }, /* R978 */
1084 { 0x0000, 0x0000 }, /* R979 */
1085 { 0x0000, 0x0000 }, /* R980 */
1086 { 0x0000, 0x0000 }, /* R981 */
1087 { 0x0000, 0x0000 }, /* R982 */
1088 { 0x0000, 0x0000 }, /* R983 */
1089 { 0x0000, 0x0000 }, /* R984 */
1090 { 0x0000, 0x0000 }, /* R985 */
1091 { 0x0000, 0x0000 }, /* R986 */
1092 { 0x0000, 0x0000 }, /* R987 */
1093 { 0x0000, 0x0000 }, /* R988 */
1094 { 0x0000, 0x0000 }, /* R989 */
1095 { 0x0000, 0x0000 }, /* R990 */
1096 { 0x0000, 0x0000 }, /* R991 */
1097 { 0x0000, 0x0000 }, /* R992 */
1098 { 0x0000, 0x0000 }, /* R993 */
1099 { 0x0000, 0x0000 }, /* R994 */
1100 { 0x0000, 0x0000 }, /* R995 */
1101 { 0x0000, 0x0000 }, /* R996 */
1102 { 0x0000, 0x0000 }, /* R997 */
1103 { 0x0000, 0x0000 }, /* R998 */
1104 { 0x0000, 0x0000 }, /* R999 */
1105 { 0x0000, 0x0000 }, /* R1000 */
1106 { 0x0000, 0x0000 }, /* R1001 */
1107 { 0x0000, 0x0000 }, /* R1002 */
1108 { 0x0000, 0x0000 }, /* R1003 */
1109 { 0x0000, 0x0000 }, /* R1004 */
1110 { 0x0000, 0x0000 }, /* R1005 */
1111 { 0x0000, 0x0000 }, /* R1006 */
1112 { 0x0000, 0x0000 }, /* R1007 */
1113 { 0x0000, 0x0000 }, /* R1008 */
1114 { 0x0000, 0x0000 }, /* R1009 */
1115 { 0x0000, 0x0000 }, /* R1010 */
1116 { 0x0000, 0x0000 }, /* R1011 */
1117 { 0x0000, 0x0000 }, /* R1012 */
1118 { 0x0000, 0x0000 }, /* R1013 */
1119 { 0x0000, 0x0000 }, /* R1014 */
1120 { 0x0000, 0x0000 }, /* R1015 */
1121 { 0x0000, 0x0000 }, /* R1016 */
1122 { 0x0000, 0x0000 }, /* R1017 */
1123 { 0x0000, 0x0000 }, /* R1018 */
1124 { 0x0000, 0x0000 }, /* R1019 */
1125 { 0x0000, 0x0000 }, /* R1020 */
1126 { 0x0000, 0x0000 }, /* R1021 */
1127 { 0x0000, 0x0000 }, /* R1022 */
1128 { 0x0000, 0x0000 }, /* R1023 */
1129 { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
1130 { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
1131 { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
1132 { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
1133 { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
1134 { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
1135 { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
1136 { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
1137 { 0x0000, 0x0000 }, /* R1032 */
1138 { 0x0000, 0x0000 }, /* R1033 */
1139 { 0x0000, 0x0000 }, /* R1034 */
1140 { 0x0000, 0x0000 }, /* R1035 */
1141 { 0x0000, 0x0000 }, /* R1036 */
1142 { 0x0000, 0x0000 }, /* R1037 */
1143 { 0x0000, 0x0000 }, /* R1038 */
1144 { 0x0000, 0x0000 }, /* R1039 */
1145 { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
1146 { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
1147 { 0x0000, 0x0000 }, /* R1042 */
1148 { 0x0000, 0x0000 }, /* R1043 */
1149 { 0x0000, 0x0000 }, /* R1044 */
1150 { 0x0000, 0x0000 }, /* R1045 */
1151 { 0x0000, 0x0000 }, /* R1046 */
1152 { 0x0000, 0x0000 }, /* R1047 */
1153 { 0x0000, 0x0000 }, /* R1048 */
1154 { 0x0000, 0x0000 }, /* R1049 */
1155 { 0x0000, 0x0000 }, /* R1050 */
1156 { 0x0000, 0x0000 }, /* R1051 */
1157 { 0x0000, 0x0000 }, /* R1052 */
1158 { 0x0000, 0x0000 }, /* R1053 */
1159 { 0x0000, 0x0000 }, /* R1054 */
1160 { 0x0000, 0x0000 }, /* R1055 */
1161 { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
1162 { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
1163 { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
1164 { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
1165 { 0x0000, 0x0000 }, /* R1060 */
1166 { 0x0000, 0x0000 }, /* R1061 */
1167 { 0x0000, 0x0000 }, /* R1062 */
1168 { 0x0000, 0x0000 }, /* R1063 */
1169 { 0x0000, 0x0000 }, /* R1064 */
1170 { 0x0000, 0x0000 }, /* R1065 */
1171 { 0x0000, 0x0000 }, /* R1066 */
1172 { 0x0000, 0x0000 }, /* R1067 */
1173 { 0x0000, 0x0000 }, /* R1068 */
1174 { 0x0000, 0x0000 }, /* R1069 */
1175 { 0x0000, 0x0000 }, /* R1070 */
1176 { 0x0000, 0x0000 }, /* R1071 */
1177 { 0x0000, 0x0000 }, /* R1072 */
1178 { 0x0000, 0x0000 }, /* R1073 */
1179 { 0x0000, 0x0000 }, /* R1074 */
1180 { 0x0000, 0x0000 }, /* R1075 */
1181 { 0x0000, 0x0000 }, /* R1076 */
1182 { 0x0000, 0x0000 }, /* R1077 */
1183 { 0x0000, 0x0000 }, /* R1078 */
1184 { 0x0000, 0x0000 }, /* R1079 */
1185 { 0x0000, 0x0000 }, /* R1080 */
1186 { 0x0000, 0x0000 }, /* R1081 */
1187 { 0x0000, 0x0000 }, /* R1082 */
1188 { 0x0000, 0x0000 }, /* R1083 */
1189 { 0x0000, 0x0000 }, /* R1084 */
1190 { 0x0000, 0x0000 }, /* R1085 */
1191 { 0x0000, 0x0000 }, /* R1086 */
1192 { 0x0000, 0x0000 }, /* R1087 */
1193 { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
1194 { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
1195 { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
1196 { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
1197 { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
1198 { 0x0000, 0x0000 }, /* R1093 */
1199 { 0x0000, 0x0000 }, /* R1094 */
1200 { 0x0000, 0x0000 }, /* R1095 */
1201 { 0x0000, 0x0000 }, /* R1096 */
1202 { 0x0000, 0x0000 }, /* R1097 */
1203 { 0x0000, 0x0000 }, /* R1098 */
1204 { 0x0000, 0x0000 }, /* R1099 */
1205 { 0x0000, 0x0000 }, /* R1100 */
1206 { 0x0000, 0x0000 }, /* R1101 */
1207 { 0x0000, 0x0000 }, /* R1102 */
1208 { 0x0000, 0x0000 }, /* R1103 */
1209 { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
1210 { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
1211 { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
1212 { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
1213 { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
1214 { 0x0000, 0x0000 }, /* R1109 */
1215 { 0x0000, 0x0000 }, /* R1110 */
1216 { 0x0000, 0x0000 }, /* R1111 */
1217 { 0x0000, 0x0000 }, /* R1112 */
1218 { 0x0000, 0x0000 }, /* R1113 */
1219 { 0x0000, 0x0000 }, /* R1114 */
1220 { 0x0000, 0x0000 }, /* R1115 */
1221 { 0x0000, 0x0000 }, /* R1116 */
1222 { 0x0000, 0x0000 }, /* R1117 */
1223 { 0x0000, 0x0000 }, /* R1118 */
1224 { 0x0000, 0x0000 }, /* R1119 */
1225 { 0x0000, 0x0000 }, /* R1120 */
1226 { 0x0000, 0x0000 }, /* R1121 */
1227 { 0x0000, 0x0000 }, /* R1122 */
1228 { 0x0000, 0x0000 }, /* R1123 */
1229 { 0x0000, 0x0000 }, /* R1124 */
1230 { 0x0000, 0x0000 }, /* R1125 */
1231 { 0x0000, 0x0000 }, /* R1126 */
1232 { 0x0000, 0x0000 }, /* R1127 */
1233 { 0x0000, 0x0000 }, /* R1128 */
1234 { 0x0000, 0x0000 }, /* R1129 */
1235 { 0x0000, 0x0000 }, /* R1130 */
1236 { 0x0000, 0x0000 }, /* R1131 */
1237 { 0x0000, 0x0000 }, /* R1132 */
1238 { 0x0000, 0x0000 }, /* R1133 */
1239 { 0x0000, 0x0000 }, /* R1134 */
1240 { 0x0000, 0x0000 }, /* R1135 */
1241 { 0x0000, 0x0000 }, /* R1136 */
1242 { 0x0000, 0x0000 }, /* R1137 */
1243 { 0x0000, 0x0000 }, /* R1138 */
1244 { 0x0000, 0x0000 }, /* R1139 */
1245 { 0x0000, 0x0000 }, /* R1140 */
1246 { 0x0000, 0x0000 }, /* R1141 */
1247 { 0x0000, 0x0000 }, /* R1142 */
1248 { 0x0000, 0x0000 }, /* R1143 */
1249 { 0x0000, 0x0000 }, /* R1144 */
1250 { 0x0000, 0x0000 }, /* R1145 */
1251 { 0x0000, 0x0000 }, /* R1146 */
1252 { 0x0000, 0x0000 }, /* R1147 */
1253 { 0x0000, 0x0000 }, /* R1148 */
1254 { 0x0000, 0x0000 }, /* R1149 */
1255 { 0x0000, 0x0000 }, /* R1150 */
1256 { 0x0000, 0x0000 }, /* R1151 */
1257 { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1258 { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1259 { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1260 { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1261 { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1262 { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1263 { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1264 { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1265 { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1266 { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1267 { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1268 { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1269 { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1270 { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1271 { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1272 { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1273 { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1274 { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1275 { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1276 { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1277 { 0x0000, 0x0000 }, /* R1172 */
1278 { 0x0000, 0x0000 }, /* R1173 */
1279 { 0x0000, 0x0000 }, /* R1174 */
1280 { 0x0000, 0x0000 }, /* R1175 */
1281 { 0x0000, 0x0000 }, /* R1176 */
1282 { 0x0000, 0x0000 }, /* R1177 */
1283 { 0x0000, 0x0000 }, /* R1178 */
1284 { 0x0000, 0x0000 }, /* R1179 */
1285 { 0x0000, 0x0000 }, /* R1180 */
1286 { 0x0000, 0x0000 }, /* R1181 */
1287 { 0x0000, 0x0000 }, /* R1182 */
1288 { 0x0000, 0x0000 }, /* R1183 */
1289 { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1290 { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1291 { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1292 { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1293 { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1294 { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1295 { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1296 { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1297 { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1298 { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1299 { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1300 { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1301 { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1302 { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1303 { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1304 { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1305 { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1306 { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1307 { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1308 { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1309 { 0x0000, 0x0000 }, /* R1204 */
1310 { 0x0000, 0x0000 }, /* R1205 */
1311 { 0x0000, 0x0000 }, /* R1206 */
1312 { 0x0000, 0x0000 }, /* R1207 */
1313 { 0x0000, 0x0000 }, /* R1208 */
1314 { 0x0000, 0x0000 }, /* R1209 */
1315 { 0x0000, 0x0000 }, /* R1210 */
1316 { 0x0000, 0x0000 }, /* R1211 */
1317 { 0x0000, 0x0000 }, /* R1212 */
1318 { 0x0000, 0x0000 }, /* R1213 */
1319 { 0x0000, 0x0000 }, /* R1214 */
1320 { 0x0000, 0x0000 }, /* R1215 */
1321 { 0x0000, 0x0000 }, /* R1216 */
1322 { 0x0000, 0x0000 }, /* R1217 */
1323 { 0x0000, 0x0000 }, /* R1218 */
1324 { 0x0000, 0x0000 }, /* R1219 */
1325 { 0x0000, 0x0000 }, /* R1220 */
1326 { 0x0000, 0x0000 }, /* R1221 */
1327 { 0x0000, 0x0000 }, /* R1222 */
1328 { 0x0000, 0x0000 }, /* R1223 */
1329 { 0x0000, 0x0000 }, /* R1224 */
1330 { 0x0000, 0x0000 }, /* R1225 */
1331 { 0x0000, 0x0000 }, /* R1226 */
1332 { 0x0000, 0x0000 }, /* R1227 */
1333 { 0x0000, 0x0000 }, /* R1228 */
1334 { 0x0000, 0x0000 }, /* R1229 */
1335 { 0x0000, 0x0000 }, /* R1230 */
1336 { 0x0000, 0x0000 }, /* R1231 */
1337 { 0x0000, 0x0000 }, /* R1232 */
1338 { 0x0000, 0x0000 }, /* R1233 */
1339 { 0x0000, 0x0000 }, /* R1234 */
1340 { 0x0000, 0x0000 }, /* R1235 */
1341 { 0x0000, 0x0000 }, /* R1236 */
1342 { 0x0000, 0x0000 }, /* R1237 */
1343 { 0x0000, 0x0000 }, /* R1238 */
1344 { 0x0000, 0x0000 }, /* R1239 */
1345 { 0x0000, 0x0000 }, /* R1240 */
1346 { 0x0000, 0x0000 }, /* R1241 */
1347 { 0x0000, 0x0000 }, /* R1242 */
1348 { 0x0000, 0x0000 }, /* R1243 */
1349 { 0x0000, 0x0000 }, /* R1244 */
1350 { 0x0000, 0x0000 }, /* R1245 */
1351 { 0x0000, 0x0000 }, /* R1246 */
1352 { 0x0000, 0x0000 }, /* R1247 */
1353 { 0x0000, 0x0000 }, /* R1248 */
1354 { 0x0000, 0x0000 }, /* R1249 */
1355 { 0x0000, 0x0000 }, /* R1250 */
1356 { 0x0000, 0x0000 }, /* R1251 */
1357 { 0x0000, 0x0000 }, /* R1252 */
1358 { 0x0000, 0x0000 }, /* R1253 */
1359 { 0x0000, 0x0000 }, /* R1254 */
1360 { 0x0000, 0x0000 }, /* R1255 */
1361 { 0x0000, 0x0000 }, /* R1256 */
1362 { 0x0000, 0x0000 }, /* R1257 */
1363 { 0x0000, 0x0000 }, /* R1258 */
1364 { 0x0000, 0x0000 }, /* R1259 */
1365 { 0x0000, 0x0000 }, /* R1260 */
1366 { 0x0000, 0x0000 }, /* R1261 */
1367 { 0x0000, 0x0000 }, /* R1262 */
1368 { 0x0000, 0x0000 }, /* R1263 */
1369 { 0x0000, 0x0000 }, /* R1264 */
1370 { 0x0000, 0x0000 }, /* R1265 */
1371 { 0x0000, 0x0000 }, /* R1266 */
1372 { 0x0000, 0x0000 }, /* R1267 */
1373 { 0x0000, 0x0000 }, /* R1268 */
1374 { 0x0000, 0x0000 }, /* R1269 */
1375 { 0x0000, 0x0000 }, /* R1270 */
1376 { 0x0000, 0x0000 }, /* R1271 */
1377 { 0x0000, 0x0000 }, /* R1272 */
1378 { 0x0000, 0x0000 }, /* R1273 */
1379 { 0x0000, 0x0000 }, /* R1274 */
1380 { 0x0000, 0x0000 }, /* R1275 */
1381 { 0x0000, 0x0000 }, /* R1276 */
1382 { 0x0000, 0x0000 }, /* R1277 */
1383 { 0x0000, 0x0000 }, /* R1278 */
1384 { 0x0000, 0x0000 }, /* R1279 */
1385 { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
1386 { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
1387 { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
1388 { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
1389 { 0x0000, 0x0000 }, /* R1284 */
1390 { 0x0000, 0x0000 }, /* R1285 */
1391 { 0x0000, 0x0000 }, /* R1286 */
1392 { 0x0000, 0x0000 }, /* R1287 */
1393 { 0x0000, 0x0000 }, /* R1288 */
1394 { 0x0000, 0x0000 }, /* R1289 */
1395 { 0x0000, 0x0000 }, /* R1290 */
1396 { 0x0000, 0x0000 }, /* R1291 */
1397 { 0x0000, 0x0000 }, /* R1292 */
1398 { 0x0000, 0x0000 }, /* R1293 */
1399 { 0x0000, 0x0000 }, /* R1294 */
1400 { 0x0000, 0x0000 }, /* R1295 */
1401 { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
1402 { 0x0000, 0x0000 }, /* R1297 */
1403 { 0x0000, 0x0000 }, /* R1298 */
1404 { 0x0000, 0x0000 }, /* R1299 */
1405 { 0x0000, 0x0000 }, /* R1300 */
1406 { 0x0000, 0x0000 }, /* R1301 */
1407 { 0x0000, 0x0000 }, /* R1302 */
1408 { 0x0000, 0x0000 }, /* R1303 */
1409 { 0x0000, 0x0000 }, /* R1304 */
1410 { 0x0000, 0x0000 }, /* R1305 */
1411 { 0x0000, 0x0000 }, /* R1306 */
1412 { 0x0000, 0x0000 }, /* R1307 */
1413 { 0x0000, 0x0000 }, /* R1308 */
1414 { 0x0000, 0x0000 }, /* R1309 */
1415 { 0x0000, 0x0000 }, /* R1310 */
1416 { 0x0000, 0x0000 }, /* R1311 */
1417 { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
1418 { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
1419 { 0x0000, 0x0000 }, /* R1314 */
1420 { 0x0000, 0x0000 }, /* R1315 */
1421 { 0x0000, 0x0000 }, /* R1316 */
1422 { 0x0000, 0x0000 }, /* R1317 */
1423 { 0x0000, 0x0000 }, /* R1318 */
1424 { 0x0000, 0x0000 }, /* R1319 */
1425 { 0x0000, 0x0000 }, /* R1320 */
1426 { 0x0000, 0x0000 }, /* R1321 */
1427 { 0x0000, 0x0000 }, /* R1322 */
1428 { 0x0000, 0x0000 }, /* R1323 */
1429 { 0x0000, 0x0000 }, /* R1324 */
1430 { 0x0000, 0x0000 }, /* R1325 */
1431 { 0x0000, 0x0000 }, /* R1326 */
1432 { 0x0000, 0x0000 }, /* R1327 */
1433 { 0x0000, 0x0000 }, /* R1328 */
1434 { 0x0000, 0x0000 }, /* R1329 */
1435 { 0x0000, 0x0000 }, /* R1330 */
1436 { 0x0000, 0x0000 }, /* R1331 */
1437 { 0x0000, 0x0000 }, /* R1332 */
1438 { 0x0000, 0x0000 }, /* R1333 */
1439 { 0x0000, 0x0000 }, /* R1334 */
1440 { 0x0000, 0x0000 }, /* R1335 */
1441 { 0x0000, 0x0000 }, /* R1336 */
1442 { 0x0000, 0x0000 }, /* R1337 */
1443 { 0x0000, 0x0000 }, /* R1338 */
1444 { 0x0000, 0x0000 }, /* R1339 */
1445 { 0x0000, 0x0000 }, /* R1340 */
1446 { 0x0000, 0x0000 }, /* R1341 */
1447 { 0x0000, 0x0000 }, /* R1342 */
1448 { 0x0000, 0x0000 }, /* R1343 */
1449 { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
1450 { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
1451 { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
1452 { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
1453 { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
1454 { 0x0000, 0x0000 }, /* R1349 */
1455 { 0x0000, 0x0000 }, /* R1350 */
1456 { 0x0000, 0x0000 }, /* R1351 */
1457 { 0x0000, 0x0000 }, /* R1352 */
1458 { 0x0000, 0x0000 }, /* R1353 */
1459 { 0x0000, 0x0000 }, /* R1354 */
1460 { 0x0000, 0x0000 }, /* R1355 */
1461 { 0x0000, 0x0000 }, /* R1356 */
1462 { 0x0000, 0x0000 }, /* R1357 */
1463 { 0x0000, 0x0000 }, /* R1358 */
1464 { 0x0000, 0x0000 }, /* R1359 */
1465 { 0x0000, 0x0000 }, /* R1360 */
1466 { 0x0000, 0x0000 }, /* R1361 */
1467 { 0x0000, 0x0000 }, /* R1362 */
1468 { 0x0000, 0x0000 }, /* R1363 */
1469 { 0x0000, 0x0000 }, /* R1364 */
1470 { 0x0000, 0x0000 }, /* R1365 */
1471 { 0x0000, 0x0000 }, /* R1366 */
1472 { 0x0000, 0x0000 }, /* R1367 */
1473 { 0x0000, 0x0000 }, /* R1368 */
1474 { 0x0000, 0x0000 }, /* R1369 */
1475 { 0x0000, 0x0000 }, /* R1370 */
1476 { 0x0000, 0x0000 }, /* R1371 */
1477 { 0x0000, 0x0000 }, /* R1372 */
1478 { 0x0000, 0x0000 }, /* R1373 */
1479 { 0x0000, 0x0000 }, /* R1374 */
1480 { 0x0000, 0x0000 }, /* R1375 */
1481 { 0x0000, 0x0000 }, /* R1376 */
1482 { 0x0000, 0x0000 }, /* R1377 */
1483 { 0x0000, 0x0000 }, /* R1378 */
1484 { 0x0000, 0x0000 }, /* R1379 */
1485 { 0x0000, 0x0000 }, /* R1380 */
1486 { 0x0000, 0x0000 }, /* R1381 */
1487 { 0x0000, 0x0000 }, /* R1382 */
1488 { 0x0000, 0x0000 }, /* R1383 */
1489 { 0x0000, 0x0000 }, /* R1384 */
1490 { 0x0000, 0x0000 }, /* R1385 */
1491 { 0x0000, 0x0000 }, /* R1386 */
1492 { 0x0000, 0x0000 }, /* R1387 */
1493 { 0x0000, 0x0000 }, /* R1388 */
1494 { 0x0000, 0x0000 }, /* R1389 */
1495 { 0x0000, 0x0000 }, /* R1390 */
1496 { 0x0000, 0x0000 }, /* R1391 */
1497 { 0x0000, 0x0000 }, /* R1392 */
1498 { 0x0000, 0x0000 }, /* R1393 */
1499 { 0x0000, 0x0000 }, /* R1394 */
1500 { 0x0000, 0x0000 }, /* R1395 */
1501 { 0x0000, 0x0000 }, /* R1396 */
1502 { 0x0000, 0x0000 }, /* R1397 */
1503 { 0x0000, 0x0000 }, /* R1398 */
1504 { 0x0000, 0x0000 }, /* R1399 */
1505 { 0x0000, 0x0000 }, /* R1400 */
1506 { 0x0000, 0x0000 }, /* R1401 */
1507 { 0x0000, 0x0000 }, /* R1402 */
1508 { 0x0000, 0x0000 }, /* R1403 */
1509 { 0x0000, 0x0000 }, /* R1404 */
1510 { 0x0000, 0x0000 }, /* R1405 */
1511 { 0x0000, 0x0000 }, /* R1406 */
1512 { 0x0000, 0x0000 }, /* R1407 */
1513 { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
1514 { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
1515 { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
1516 { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
1517 { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
1518 { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
1519 { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
1520 { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
1521 { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
1522 { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
1523 { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
1524 { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
1525 { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
1526 { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
1527 { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
1528 { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
1529 { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
1530 { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
1531 { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
1532 { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
1533 { 0x0000, 0x0000 }, /* R1428 */
1534 { 0x0000, 0x0000 }, /* R1429 */
1535 { 0x0000, 0x0000 }, /* R1430 */
1536 { 0x0000, 0x0000 }, /* R1431 */
1537 { 0x0000, 0x0000 }, /* R1432 */
1538 { 0x0000, 0x0000 }, /* R1433 */
1539 { 0x0000, 0x0000 }, /* R1434 */
1540 { 0x0000, 0x0000 }, /* R1435 */
1541 { 0x0000, 0x0000 }, /* R1436 */
1542 { 0x0000, 0x0000 }, /* R1437 */
1543 { 0x0000, 0x0000 }, /* R1438 */
1544 { 0x0000, 0x0000 }, /* R1439 */
1545 { 0x0000, 0x0000 }, /* R1440 */
1546 { 0x0000, 0x0000 }, /* R1441 */
1547 { 0x0000, 0x0000 }, /* R1442 */
1548 { 0x0000, 0x0000 }, /* R1443 */
1549 { 0x0000, 0x0000 }, /* R1444 */
1550 { 0x0000, 0x0000 }, /* R1445 */
1551 { 0x0000, 0x0000 }, /* R1446 */
1552 { 0x0000, 0x0000 }, /* R1447 */
1553 { 0x0000, 0x0000 }, /* R1448 */
1554 { 0x0000, 0x0000 }, /* R1449 */
1555 { 0x0000, 0x0000 }, /* R1450 */
1556 { 0x0000, 0x0000 }, /* R1451 */
1557 { 0x0000, 0x0000 }, /* R1452 */
1558 { 0x0000, 0x0000 }, /* R1453 */
1559 { 0x0000, 0x0000 }, /* R1454 */
1560 { 0x0000, 0x0000 }, /* R1455 */
1561 { 0x0000, 0x0000 }, /* R1456 */
1562 { 0x0000, 0x0000 }, /* R1457 */
1563 { 0x0000, 0x0000 }, /* R1458 */
1564 { 0x0000, 0x0000 }, /* R1459 */
1565 { 0x0000, 0x0000 }, /* R1460 */
1566 { 0x0000, 0x0000 }, /* R1461 */
1567 { 0x0000, 0x0000 }, /* R1462 */
1568 { 0x0000, 0x0000 }, /* R1463 */
1569 { 0x0000, 0x0000 }, /* R1464 */
1570 { 0x0000, 0x0000 }, /* R1465 */
1571 { 0x0000, 0x0000 }, /* R1466 */
1572 { 0x0000, 0x0000 }, /* R1467 */
1573 { 0x0000, 0x0000 }, /* R1468 */
1574 { 0x0000, 0x0000 }, /* R1469 */
1575 { 0x0000, 0x0000 }, /* R1470 */
1576 { 0x0000, 0x0000 }, /* R1471 */
1577 { 0x0000, 0x0000 }, /* R1472 */
1578 { 0x0000, 0x0000 }, /* R1473 */
1579 { 0x0000, 0x0000 }, /* R1474 */
1580 { 0x0000, 0x0000 }, /* R1475 */
1581 { 0x0000, 0x0000 }, /* R1476 */
1582 { 0x0000, 0x0000 }, /* R1477 */
1583 { 0x0000, 0x0000 }, /* R1478 */
1584 { 0x0000, 0x0000 }, /* R1479 */
1585 { 0x0000, 0x0000 }, /* R1480 */
1586 { 0x0000, 0x0000 }, /* R1481 */
1587 { 0x0000, 0x0000 }, /* R1482 */
1588 { 0x0000, 0x0000 }, /* R1483 */
1589 { 0x0000, 0x0000 }, /* R1484 */
1590 { 0x0000, 0x0000 }, /* R1485 */
1591 { 0x0000, 0x0000 }, /* R1486 */
1592 { 0x0000, 0x0000 }, /* R1487 */
1593 { 0x0000, 0x0000 }, /* R1488 */
1594 { 0x0000, 0x0000 }, /* R1489 */
1595 { 0x0000, 0x0000 }, /* R1490 */
1596 { 0x0000, 0x0000 }, /* R1491 */
1597 { 0x0000, 0x0000 }, /* R1492 */
1598 { 0x0000, 0x0000 }, /* R1493 */
1599 { 0x0000, 0x0000 }, /* R1494 */
1600 { 0x0000, 0x0000 }, /* R1495 */
1601 { 0x0000, 0x0000 }, /* R1496 */
1602 { 0x0000, 0x0000 }, /* R1497 */
1603 { 0x0000, 0x0000 }, /* R1498 */
1604 { 0x0000, 0x0000 }, /* R1499 */
1605 { 0x0000, 0x0000 }, /* R1500 */
1606 { 0x0000, 0x0000 }, /* R1501 */
1607 { 0x0000, 0x0000 }, /* R1502 */
1608 { 0x0000, 0x0000 }, /* R1503 */
1609 { 0x0000, 0x0000 }, /* R1504 */
1610 { 0x0000, 0x0000 }, /* R1505 */
1611 { 0x0000, 0x0000 }, /* R1506 */
1612 { 0x0000, 0x0000 }, /* R1507 */
1613 { 0x0000, 0x0000 }, /* R1508 */
1614 { 0x0000, 0x0000 }, /* R1509 */
1615 { 0x0000, 0x0000 }, /* R1510 */
1616 { 0x0000, 0x0000 }, /* R1511 */
1617 { 0x0000, 0x0000 }, /* R1512 */
1618 { 0x0000, 0x0000 }, /* R1513 */
1619 { 0x0000, 0x0000 }, /* R1514 */
1620 { 0x0000, 0x0000 }, /* R1515 */
1621 { 0x0000, 0x0000 }, /* R1516 */
1622 { 0x0000, 0x0000 }, /* R1517 */
1623 { 0x0000, 0x0000 }, /* R1518 */
1624 { 0x0000, 0x0000 }, /* R1519 */
1625 { 0x0000, 0x0000 }, /* R1520 */
1626 { 0x0000, 0x0000 }, /* R1521 */
1627 { 0x0000, 0x0000 }, /* R1522 */
1628 { 0x0000, 0x0000 }, /* R1523 */
1629 { 0x0000, 0x0000 }, /* R1524 */
1630 { 0x0000, 0x0000 }, /* R1525 */
1631 { 0x0000, 0x0000 }, /* R1526 */
1632 { 0x0000, 0x0000 }, /* R1527 */
1633 { 0x0000, 0x0000 }, /* R1528 */
1634 { 0x0000, 0x0000 }, /* R1529 */
1635 { 0x0000, 0x0000 }, /* R1530 */
1636 { 0x0000, 0x0000 }, /* R1531 */
1637 { 0x0000, 0x0000 }, /* R1532 */
1638 { 0x0000, 0x0000 }, /* R1533 */
1639 { 0x0000, 0x0000 }, /* R1534 */
1640 { 0x0000, 0x0000 }, /* R1535 */
1641 { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
1642 { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
1643 { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
1644 { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
1645 { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
1646 { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
1647 { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1648 { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1649 { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1650 { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1651 { 0x0000, 0x0000 }, /* R1546 */
1652 { 0x0000, 0x0000 }, /* R1547 */
1653 { 0x0000, 0x0000 }, /* R1548 */
1654 { 0x0000, 0x0000 }, /* R1549 */
1655 { 0x0000, 0x0000 }, /* R1550 */
1656 { 0x0000, 0x0000 }, /* R1551 */
1657 { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
1658 { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
1659 { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
1660 { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
1661 { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
1662 { 0x0000, 0x0000 }, /* R1557 */
1663 { 0x0000, 0x0000 }, /* R1558 */
1664 { 0x0000, 0x0000 }, /* R1559 */
1665 { 0x0000, 0x0000 }, /* R1560 */
1666 { 0x0000, 0x0000 }, /* R1561 */
1667 { 0x0000, 0x0000 }, /* R1562 */
1668 { 0x0000, 0x0000 }, /* R1563 */
1669 { 0x0000, 0x0000 }, /* R1564 */
1670 { 0x0000, 0x0000 }, /* R1565 */
1671 { 0x0000, 0x0000 }, /* R1566 */
1672 { 0x0000, 0x0000 }, /* R1567 */
1673 { 0x0003, 0x0003 }, /* R1568 - Oversampling */
1674 { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
1675 };
1676
1677 static int wm8994_readable(unsigned int reg)
1678 { 116 {
1679 switch (reg) { 117 switch (reg) {
1680 case WM8994_GPIO_1: 118 case WM8994_GPIO_1:
1681 case WM8994_GPIO_2: 119 case WM8994_GPIO_2:
1682 case WM8994_GPIO_3: 120 case WM8994_GPIO_3:
1683 case WM8994_GPIO_4: 121 case WM8994_GPIO_4:
1684 case WM8994_GPIO_5: 122 case WM8994_GPIO_5:
1685 case WM8994_GPIO_6: 123 case WM8994_GPIO_6:
1686 case WM8994_GPIO_7: 124 case WM8994_GPIO_7:
1687 case WM8994_GPIO_8: 125 case WM8994_GPIO_8:
1688 case WM8994_GPIO_9: 126 case WM8994_GPIO_9:
1689 case WM8994_GPIO_10: 127 case WM8994_GPIO_10:
1690 case WM8994_GPIO_11: 128 case WM8994_GPIO_11:
1691 case WM8994_INTERRUPT_STATUS_1: 129 case WM8994_INTERRUPT_STATUS_1:
1692 case WM8994_INTERRUPT_STATUS_2: 130 case WM8994_INTERRUPT_STATUS_2:
1693 case WM8994_INTERRUPT_RAW_STATUS_2: 131 case WM8994_INTERRUPT_RAW_STATUS_2:
1694 return 1; 132 return 1;
1695 default: 133 default:
1696 break; 134 break;
1697 } 135 }
1698 136
1699 » if (reg >= ARRAY_SIZE(access_masks)) 137 » if (reg >= WM8994_CACHE_SIZE)
1700 return 0; 138 return 0;
1701 » return access_masks[reg].readable != 0; 139 » return wm8994_access_masks[reg].readable != 0;
1702 } 140 }
1703 141
1704 static int wm8994_volatile(unsigned int reg) 142 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
1705 { 143 {
1706 » if (reg >= WM8994_REG_CACHE_SIZE) 144 » if (reg >= WM8994_CACHE_SIZE)
1707 return 1; 145 return 1;
1708 146
1709 switch (reg) { 147 switch (reg) {
1710 case WM8994_SOFTWARE_RESET: 148 case WM8994_SOFTWARE_RESET:
1711 case WM8994_CHIP_REVISION: 149 case WM8994_CHIP_REVISION:
1712 case WM8994_DC_SERVO_1: 150 case WM8994_DC_SERVO_1:
1713 case WM8994_DC_SERVO_READBACK: 151 case WM8994_DC_SERVO_READBACK:
1714 case WM8994_RATE_STATUS: 152 case WM8994_RATE_STATUS:
1715 case WM8994_LDO_1: 153 case WM8994_LDO_1:
1716 case WM8994_LDO_2: 154 case WM8994_LDO_2:
155 case WM8958_DSP2_EXECCONTROL:
156 case WM8958_MIC_DETECT_3:
1717 return 1; 157 return 1;
1718 default: 158 default:
1719 return 0; 159 return 0;
1720 } 160 }
1721 } 161 }
1722 162
1723 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 163 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1724 unsigned int value) 164 unsigned int value)
1725 { 165 {
1726 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 166 » int ret;
1727 167
1728 BUG_ON(reg > WM8994_MAX_REGISTER); 168 BUG_ON(reg > WM8994_MAX_REGISTER);
1729 169
1730 » if (!wm8994_volatile(reg)) 170 » if (!wm8994_volatile(codec, reg)) {
1731 » » wm8994->reg_cache[reg] = value; 171 » » ret = snd_soc_cache_write(codec, reg, value);
1732 172 » » if (ret != 0)
1733 » dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); 173 » » » dev_err(codec->dev, "Cache write to %x failed: %d\n",
174 » » » » reg, ret);
175 » }
1734 176
1735 return wm8994_reg_write(codec->control_data, reg, value); 177 return wm8994_reg_write(codec->control_data, reg, value);
1736 } 178 }
1737 179
1738 static unsigned int wm8994_read(struct snd_soc_codec *codec, 180 static unsigned int wm8994_read(struct snd_soc_codec *codec,
1739 unsigned int reg) 181 unsigned int reg)
1740 { 182 {
1741 » u16 *reg_cache = codec->reg_cache; 183 » unsigned int val;
184 » int ret;
1742 185
1743 BUG_ON(reg > WM8994_MAX_REGISTER); 186 BUG_ON(reg > WM8994_MAX_REGISTER);
1744 187
1745 » if (wm8994_volatile(reg)) 188 » if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
1746 » » return wm8994_reg_read(codec->control_data, reg); 189 » reg < codec->driver->reg_cache_size) {
1747 » else 190 » » ret = snd_soc_cache_read(codec, reg, &val);
1748 » » return reg_cache[reg]; 191 » » if (ret >= 0)
192 » » » return val;
193 » » else
194 » » » dev_err(codec->dev, "Cache read from %x failed: %d\n",
195 » » » » reg, ret);
196 » }
197
198 » return wm8994_reg_read(codec->control_data, reg);
1749 } 199 }
1750 200
1751 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 201 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
1752 { 202 {
1753 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 203 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1754 int rate; 204 int rate;
1755 int reg1 = 0; 205 int reg1 = 0;
1756 int offset; 206 int offset;
1757 207
1758 if (aif) 208 if (aif)
(...skipping 71 matching lines...) Expand 10 before | Expand all | Expand 10 after
1830 new = 0; 280 new = 0;
1831 281
1832 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; 282 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
1833 283
1834 /* If there's no change then we're done. */ 284 /* If there's no change then we're done. */
1835 if (old == new) 285 if (old == new)
1836 return 0; 286 return 0;
1837 287
1838 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 288 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1839 289
1840 » snd_soc_dapm_sync(codec); 290 » snd_soc_dapm_sync(&codec->dapm);
1841 291
1842 return 0; 292 return 0;
1843 } 293 }
1844 294
1845 static int check_clk_sys(struct snd_soc_dapm_widget *source, 295 static int check_clk_sys(struct snd_soc_dapm_widget *source,
1846 struct snd_soc_dapm_widget *sink) 296 struct snd_soc_dapm_widget *sink)
1847 { 297 {
1848 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 298 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
1849 const char *clk; 299 const char *clk;
1850 300
1851 /* Check what we're currently using for CLK_SYS */ 301 /* Check what we're currently using for CLK_SYS */
1852 if (reg & WM8994_SYSCLK_SRC) 302 if (reg & WM8994_SYSCLK_SRC)
1853 clk = "AIF2CLK"; 303 clk = "AIF2CLK";
1854 else 304 else
1855 clk = "AIF1CLK"; 305 clk = "AIF1CLK";
1856 306
1857 return strcmp(source->name, clk) == 0; 307 return strcmp(source->name, clk) == 0;
1858 } 308 }
1859 309
1860 static const char *sidetone_hpf_text[] = { 310 static const char *sidetone_hpf_text[] = {
1861 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 311 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
1862 }; 312 };
1863 313
1864 static const struct soc_enum sidetone_hpf = 314 static const struct soc_enum sidetone_hpf =
1865 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 315 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1866 316
317 static const char *adc_hpf_text[] = {
318 "HiFi", "Voice 1", "Voice 2", "Voice 3"
319 };
320
321 static const struct soc_enum aif1adc1_hpf =
322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
323
324 static const struct soc_enum aif1adc2_hpf =
325 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
326
327 static const struct soc_enum aif2adc_hpf =
328 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
329
1867 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 330 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1868 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 331 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1869 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 332 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1870 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 333 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
1871 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 334 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1872 335
1873 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 336 #define WM8994_DRC_SWITCH(xname, reg, shift) \
1874 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 337 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1875 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 338 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
1876 .put = wm8994_put_drc_sw, \ 339 .put = wm8994_put_drc_sw, \
(...skipping 187 matching lines...) Expand 10 before | Expand all | Expand 10 after
2064 { 527 {
2065 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 528 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2066 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec); 529 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
2067 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 530 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2068 531
2069 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 532 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
2070 533
2071 return 0; 534 return 0;
2072 } 535 }
2073 536
2074 static const char *aifdac_src_text[] = { 537 static const char *aif_chan_src_text[] = {
2075 "Left", "Right" 538 "Left", "Right"
2076 }; 539 };
2077 540
541 static const struct soc_enum aif1adcl_src =
542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
543
544 static const struct soc_enum aif1adcr_src =
545 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
546
547 static const struct soc_enum aif2adcl_src =
548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
549
550 static const struct soc_enum aif2adcr_src =
551 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
552
2078 static const struct soc_enum aif1dacl_src = 553 static const struct soc_enum aif1dacl_src =
2079 » SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aifdac_src_text); 554 » SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
2080 555
2081 static const struct soc_enum aif1dacr_src = 556 static const struct soc_enum aif1dacr_src =
2082 » SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aifdac_src_text); 557 » SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
2083 558
2084 static const struct soc_enum aif2dacl_src = 559 static const struct soc_enum aif2dacl_src =
2085 » SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aifdac_src_text); 560 » SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
2086 561
2087 static const struct soc_enum aif2dacr_src = 562 static const struct soc_enum aif2dacr_src =
2088 » SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aifdac_src_text); 563 » SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
564
565 static const char *osr_text[] = {
566 » "Low Power", "High Performance",
567 };
568
569 static const struct soc_enum dac_osr =
570 » SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
571
572 static const struct soc_enum adc_osr =
573 » SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
574
575 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
576 {
577 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
578 » struct wm8994_pdata *pdata = wm8994->pdata;
579 » int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
580 » int ena, reg, aif, i;
581
582 » switch (mbc) {
583 » case 0:
584 » » pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
585 » » aif = 0;
586 » » break;
587 » case 1:
588 » » pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
589 » » aif = 0;
590 » » break;
591 » case 2:
592 » » pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
593 » » aif = 1;
594 » » break;
595 » default:
596 » » BUG();
597 » » return;
598 » }
599
600 » /* We can only enable the MBC if the AIF is enabled and we
601 » * want it to be enabled. */
602 » ena = pwr_reg && wm8994->mbc_ena[mbc];
603
604 » reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
605
606 » dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
607 » » mbc, start, pwr_reg, reg);
608
609 » if (start && ena) {
610 » » /* If the DSP is already running then noop */
611 » » if (reg & WM8958_DSP2_ENA)
612 » » » return;
613
614 » » /* Switch the clock over to the appropriate AIF */
615 » » snd_soc_update_bits(codec, WM8994_CLOCKING_1,
616 » » » » WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
617 » » » » aif << WM8958_DSP2CLK_SRC_SHIFT |
618 » » » » WM8958_DSP2CLK_ENA);
619
620 » » snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
621 » » » » WM8958_DSP2_ENA, WM8958_DSP2_ENA);
622
623 » » /* If we've got user supplied MBC settings use them */
624 » » if (pdata && pdata->num_mbc_cfgs) {
625 » » » struct wm8958_mbc_cfg *cfg
626 » » » » = &pdata->mbc_cfgs[wm8994->mbc_cfg];
627
628 » » » for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
629 » » » » snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
630 » » » » » cfg->coeff_regs[i]);
631
632 » » » for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
633 » » » » snd_soc_write(codec,
634 » » » » » i + WM8958_MBC_BAND_2_LOWER_CUTOFF _C1_1,
635 » » » » » cfg->cutoff_regs[i]);
636 » » }
637
638 » » /* Run the DSP */
639 » » snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
640 » » » WM8958_DSP2_RUNR);
641
642 » » /* And we're off! */
643 » » snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
644 » » » » WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
645 » » » » mbc << WM8958_MBC_SEL_SHIFT |
646 » » » » WM8958_MBC_ENA);
647 » } else {
648 » » /* If the DSP is already stopped then noop */
649 » » if (!(reg & WM8958_DSP2_ENA))
650 » » » return;
651
652 » » snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
653 » » » » WM8958_MBC_ENA, 0);»
654 » » snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
655 » » » » WM8958_DSP2_ENA, 0);
656 » » snd_soc_update_bits(codec, WM8994_CLOCKING_1,
657 » » » » WM8958_DSP2CLK_ENA, 0);
658 » }
659 }
660
661 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
662 » » struct snd_kcontrol *kcontrol, int event)
663 {
664 » struct snd_soc_codec *codec = w->codec;
665 » int mbc;
666
667 » switch (w->shift) {
668 » case 13:
669 » case 12:
670 » » mbc = 2;
671 » » break;
672 » case 11:
673 » case 10:
674 » » mbc = 1;
675 » » break;
676 » case 9:
677 » case 8:
678 » » mbc = 0;
679 » » break;
680 » default:
681 » » BUG();
682 » » return -EINVAL;
683 » }
684
685 » switch (event) {
686 » case SND_SOC_DAPM_POST_PMU:
687 » » wm8958_mbc_apply(codec, mbc, 1);
688 » » break;
689 » case SND_SOC_DAPM_POST_PMD:
690 » » wm8958_mbc_apply(codec, mbc, 0);
691 » » break;
692 » }
693
694 » return 0;
695 }
696
697 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
698 » » » struct snd_ctl_elem_value *ucontrol)
699 {
700 » struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
701 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702 » struct wm8994_pdata *pdata = wm8994->pdata;
703 » int value = ucontrol->value.integer.value[0];
704 » int reg;
705
706 » /* Don't allow on the fly reconfiguration */
707 » reg = snd_soc_read(codec, WM8994_CLOCKING_1);
708 » if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
709 » » return -EBUSY;
710
711 » if (value >= pdata->num_mbc_cfgs)
712 » » return -EINVAL;
713
714 » wm8994->mbc_cfg = value;
715
716 » return 0;
717 }
718
719 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
720 » » » struct snd_ctl_elem_value *ucontrol)
721 {
722 » struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
723 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
724
725 » ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
726
727 » return 0;
728 }
729
730 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
731 » » » struct snd_ctl_elem_info *uinfo)
732 {
733 » uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
734 » uinfo->count = 1;
735 » uinfo->value.integer.min = 0;
736 » uinfo->value.integer.max = 1;
737 » return 0;
738 }
739
740 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
741 » » » struct snd_ctl_elem_value *ucontrol)
742 {
743 » int mbc = kcontrol->private_value;
744 » struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
745 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
746
747 » ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
748
749 » return 0;
750 }
751
752 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
753 » » » struct snd_ctl_elem_value *ucontrol)
754 {
755 » int mbc = kcontrol->private_value;
756 » int i;
757 » struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
758 » struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
759
760 » if (ucontrol->value.integer.value[0] > 1)
761 » » return -EINVAL;
762
763 » for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
764 » » if (mbc != i && wm8994->mbc_ena[i]) {
765 » » » dev_dbg(codec->dev, "MBC %d active already\n", mbc);
766 » » » return -EBUSY;
767 » » }
768 » }
769
770 » wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
771
772 » wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
773
774 » return 0;
775 }
776
777 #define WM8958_MBC_SWITCH(xname, xval) {\
778 » .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
779 » .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
780 » .info = wm8958_mbc_info, \
781 » .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
782 » .private_value = xval }
2089 783
2090 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 784 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2091 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 785 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
2092 WM8994_AIF1_ADC1_RIGHT_VOLUME, 786 WM8994_AIF1_ADC1_RIGHT_VOLUME,
2093 1, 119, 0, digital_tlv), 787 1, 119, 0, digital_tlv),
2094 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 788 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
2095 WM8994_AIF1_ADC2_RIGHT_VOLUME, 789 WM8994_AIF1_ADC2_RIGHT_VOLUME,
2096 1, 119, 0, digital_tlv), 790 1, 119, 0, digital_tlv),
2097 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 791 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2098 WM8994_AIF2_ADC_RIGHT_VOLUME, 792 WM8994_AIF2_ADC_RIGHT_VOLUME,
2099 1, 119, 0, digital_tlv), 793 1, 119, 0, digital_tlv),
2100 794
795 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
796 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
797 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
798 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
799
2101 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 800 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
2102 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 801 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
2103 SOC_ENUM("AIF2DACL Source", aif1dacl_src), 802 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
2104 SOC_ENUM("AIF2DACR Source", aif1dacr_src), 803 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
2105 804
2106 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 805 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2107 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 806 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2108 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 807 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
2109 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 808 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2110 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 809 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
2111 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 810 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2112 811
2113 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 812 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
2114 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 813 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
(...skipping 18 matching lines...) Expand all
2133 5, 12, 0, st_tlv), 832 5, 12, 0, st_tlv),
2134 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 833 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
2135 0, 12, 0, st_tlv), 834 0, 12, 0, st_tlv),
2136 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 835 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2137 5, 12, 0, st_tlv), 836 5, 12, 0, st_tlv),
2138 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 837 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2139 0, 12, 0, st_tlv), 838 0, 12, 0, st_tlv),
2140 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 839 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2141 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 840 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2142 841
842 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
843 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
844
845 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
846 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
847
848 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
849 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
850
851 SOC_ENUM("ADC OSR", adc_osr),
852 SOC_ENUM("DAC OSR", dac_osr),
853
2143 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 854 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2144 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 855 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2145 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 856 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
2146 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 857 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
2147 858
2148 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 859 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
2149 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 860 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2150 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 861 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
2151 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 862 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
2152 863
2153 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 864 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
2154 6, 1, 1, wm_hubs_spkmix_tlv), 865 6, 1, 1, wm_hubs_spkmix_tlv),
2155 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 866 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
2156 2, 1, 1, wm_hubs_spkmix_tlv), 867 2, 1, 1, wm_hubs_spkmix_tlv),
2157 868
2158 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 869 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
2159 6, 1, 1, wm_hubs_spkmix_tlv), 870 6, 1, 1, wm_hubs_spkmix_tlv),
2160 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 871 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2161 2, 1, 1, wm_hubs_spkmix_tlv), 872 2, 1, 1, wm_hubs_spkmix_tlv),
2162 873
2163 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 874 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2164 10, 15, 0, wm8994_3d_tlv), 875 10, 15, 0, wm8994_3d_tlv),
2165 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 876 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
2166 8, 1, 0), 877 8, 1, 0),
2167 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 878 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2168 10, 15, 0, wm8994_3d_tlv), 879 10, 15, 0, wm8994_3d_tlv),
2169 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 880 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2170 8, 1, 0), 881 8, 1, 0),
2171 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 882 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
2172 10, 15, 0, wm8994_3d_tlv), 883 10, 15, 0, wm8994_3d_tlv),
2173 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 884 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
2174 8, 1, 0), 885 8, 1, 0),
2175 }; 886 };
2176 887
2177 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 888 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
2178 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 889 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
2179 eq_tlv), 890 eq_tlv),
2180 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 891 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
2181 eq_tlv), 892 eq_tlv),
2182 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 893 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
2183 eq_tlv), 894 eq_tlv),
(...skipping 18 matching lines...) Expand all
2202 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 913 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
2203 eq_tlv), 914 eq_tlv),
2204 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 915 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
2205 eq_tlv), 916 eq_tlv),
2206 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 917 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
2207 eq_tlv), 918 eq_tlv),
2208 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 919 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2209 eq_tlv), 920 eq_tlv),
2210 }; 921 };
2211 922
923 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
924 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
925 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
926 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
927 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
928 };
929
2212 static int clk_sys_event(struct snd_soc_dapm_widget *w, 930 static int clk_sys_event(struct snd_soc_dapm_widget *w,
2213 struct snd_kcontrol *kcontrol, int event) 931 struct snd_kcontrol *kcontrol, int event)
2214 { 932 {
2215 struct snd_soc_codec *codec = w->codec; 933 struct snd_soc_codec *codec = w->codec;
2216 934
2217 switch (event) { 935 switch (event) {
2218 case SND_SOC_DAPM_PRE_PMU: 936 case SND_SOC_DAPM_PRE_PMU:
2219 return configure_clock(codec); 937 return configure_clock(codec);
2220 938
2221 case SND_SOC_DAPM_POST_PMD: 939 case SND_SOC_DAPM_POST_PMD:
2222 configure_clock(codec); 940 configure_clock(codec);
2223 break; 941 break;
2224 } 942 }
2225 943
2226 return 0; 944 return 0;
2227 } 945 }
2228 946
2229 static void wm8994_update_class_w(struct snd_soc_codec *codec) 947 static void wm8994_update_class_w(struct snd_soc_codec *codec)
2230 { 948 {
949 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2231 int enable = 1; 950 int enable = 1;
2232 int source = 0; /* GCC flow analysis can't track enable */ 951 int source = 0; /* GCC flow analysis can't track enable */
2233 int reg, reg_r; 952 int reg, reg_r;
2234 953
2235 /* Only support direct DAC->headphone paths */ 954 /* Only support direct DAC->headphone paths */
2236 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); 955 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
2237 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { 956 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
2238 dev_vdbg(codec->dev, "HPL connected to output mixer\n"); 957 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
2239 enable = 0; 958 enable = 0;
2240 } 959 }
(...skipping 30 matching lines...) Expand all
2271 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 990 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
2272 enable = 0; 991 enable = 0;
2273 } 992 }
2274 993
2275 if (enable) { 994 if (enable) {
2276 dev_dbg(codec->dev, "Class W enabled\n"); 995 dev_dbg(codec->dev, "Class W enabled\n");
2277 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 996 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2278 WM8994_CP_DYN_PWR | 997 WM8994_CP_DYN_PWR |
2279 WM8994_CP_DYN_SRC_SEL_MASK, 998 WM8994_CP_DYN_SRC_SEL_MASK,
2280 source | WM8994_CP_DYN_PWR); 999 source | WM8994_CP_DYN_PWR);
1000 wm8994->hubs.class_w = true;
2281 1001
2282 } else { 1002 } else {
2283 dev_dbg(codec->dev, "Class W disabled\n"); 1003 dev_dbg(codec->dev, "Class W disabled\n");
2284 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1004 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2285 WM8994_CP_DYN_PWR, 0); 1005 WM8994_CP_DYN_PWR, 0);
1006 wm8994->hubs.class_w = false;
2286 } 1007 }
2287 } 1008 }
2288 1009
1010 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1011 struct snd_kcontrol *kcontrol, int event)
1012 {
1013 struct snd_soc_codec *codec = w->codec;
1014 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1015
1016 switch (event) {
1017 case SND_SOC_DAPM_PRE_PMU:
1018 if (wm8994->aif1clk_enable)
1019 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1020 WM8994_AIF1CLK_ENA_MASK,
1021 WM8994_AIF1CLK_ENA);
1022 if (wm8994->aif2clk_enable)
1023 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1024 WM8994_AIF2CLK_ENA_MASK,
1025 WM8994_AIF2CLK_ENA);
1026 break;
1027 }
1028
1029 return 0;
1030 }
1031
1032 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033 struct snd_kcontrol *kcontrol, int event)
1034 {
1035 struct snd_soc_codec *codec = w->codec;
1036 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038 switch (event) {
1039 case SND_SOC_DAPM_POST_PMD:
1040 if (wm8994->aif1clk_enable) {
1041 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042 WM8994_AIF1CLK_ENA_MASK, 0);
1043 wm8994->aif1clk_enable = 0;
1044 }
1045 if (wm8994->aif2clk_enable) {
1046 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047 WM8994_AIF2CLK_ENA_MASK, 0);
1048 wm8994->aif2clk_enable = 0;
1049 }
1050 break;
1051 }
1052
1053 return 0;
1054 }
1055
1056 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057 struct snd_kcontrol *kcontrol, int event)
1058 {
1059 struct snd_soc_codec *codec = w->codec;
1060 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062 switch (event) {
1063 case SND_SOC_DAPM_PRE_PMU:
1064 wm8994->aif1clk_enable = 1;
1065 break;
1066 }
1067
1068 return 0;
1069 }
1070
1071 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1072 struct snd_kcontrol *kcontrol, int event)
1073 {
1074 struct snd_soc_codec *codec = w->codec;
1075 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1076
1077 switch (event) {
1078 case SND_SOC_DAPM_PRE_PMU:
1079 wm8994->aif2clk_enable = 1;
1080 break;
1081 }
1082
1083 return 0;
1084 }
1085
1086 static int dac_ev(struct snd_soc_dapm_widget *w,
1087 struct snd_kcontrol *kcontrol, int event)
1088 {
1089 struct snd_soc_codec *codec = w->codec;
1090 unsigned int mask = 1 << w->shift;
1091
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1093 mask, mask);
1094 return 0;
1095 }
1096
2289 static const char *hp_mux_text[] = { 1097 static const char *hp_mux_text[] = {
2290 "Mixer", 1098 "Mixer",
2291 "DAC", 1099 "DAC",
2292 }; 1100 };
2293 1101
2294 #define WM8994_HP_ENUM(xname, xenum) \ 1102 #define WM8994_HP_ENUM(xname, xenum) \
2295 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1103 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2296 .info = snd_soc_info_enum_double, \ 1104 .info = snd_soc_info_enum_double, \
2297 .get = snd_soc_dapm_get_enum_double, \ 1105 .get = snd_soc_dapm_get_enum_double, \
2298 .put = wm8994_put_hp_enum, \ 1106 .put = wm8994_put_hp_enum, \
(...skipping 206 matching lines...) Expand 10 before | Expand all | Expand 10 after
2505 "AIF2ADCDAT", "AIF3DACDAT", 1313 "AIF2ADCDAT", "AIF3DACDAT",
2506 }; 1314 };
2507 1315
2508 static const struct soc_enum aif2adc_enum = 1316 static const struct soc_enum aif2adc_enum =
2509 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1317 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
2510 1318
2511 static const struct snd_kcontrol_new aif2adc_mux = 1319 static const struct snd_kcontrol_new aif2adc_mux =
2512 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1320 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2513 1321
2514 static const char *aif3adc_text[] = { 1322 static const char *aif3adc_text[] = {
2515 » "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", 1323 » "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
2516 }; 1324 };
2517 1325
2518 static const struct soc_enum aif3adc_enum = 1326 static const struct soc_enum wm8994_aif3adc_enum =
2519 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1327 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2520 1328
2521 static const struct snd_kcontrol_new aif3adc_mux = 1329 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
2522 » SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); 1330 » SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1331
1332 static const struct soc_enum wm8958_aif3adc_enum =
1333 » SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1334
1335 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1336 » SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1337
1338 static const char *mono_pcm_out_text[] = {
1339 » "None", "AIF2ADCL", "AIF2ADCR",
1340 };
1341
1342 static const struct soc_enum mono_pcm_out_enum =
1343 » SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1344
1345 static const struct snd_kcontrol_new mono_pcm_out_mux =
1346 » SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1347
1348 static const char *aif2dac_src_text[] = {
1349 » "AIF2", "AIF3",
1350 };
1351
1352 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1353 static const struct soc_enum aif2dacl_src_enum =
1354 » SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1355
1356 static const struct snd_kcontrol_new aif2dacl_src_mux =
1357 » SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1358
1359 static const struct soc_enum aif2dacr_src_enum =
1360 » SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1361
1362 static const struct snd_kcontrol_new aif2dacr_src_mux =
1363 » SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1364
1365 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1366 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1367 » SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1368 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1369 » SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1370
1371 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1372 » late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1373 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1374 » late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1375 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1376 » late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1377 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1378 » late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1379
1380 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1381 };
1382
1383 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1384 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1385 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1386 };
1387
1388 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1389 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1390 » dac_ev, SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1392 » dac_ev, SND_SOC_DAPM_PRE_PMU),
1393 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1394 » dac_ev, SND_SOC_DAPM_PRE_PMU),
1395 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1396 » dac_ev, SND_SOC_DAPM_PRE_PMU),
1397 };
1398
1399 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1400 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1401 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1402 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1403 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1404 };
2523 1405
2524 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1406 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2525 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1407 SND_SOC_DAPM_INPUT("DMIC1DAT"),
2526 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1408 SND_SOC_DAPM_INPUT("DMIC2DAT"),
2527 SND_SOC_DAPM_INPUT("Clock"), 1409 SND_SOC_DAPM_INPUT("Clock"),
2528 1410
2529 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1411 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
2530 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1412 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2531 1413
2532 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), 1414 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
2533 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 1415 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
2534 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 1416 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
2535 1417
2536 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 1418 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
2537 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), 1419 » » 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1420 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1421 » » 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1422 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1423 » » WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1424 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1425 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1426 » » WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1427 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2538 1428
2539 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 1429 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
2540 » » 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2541 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
2542 » » 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2543 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
2544 » » WM8994_POWER_MANAGEMENT_5, 9, 0),
2545 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
2546 » » WM8994_POWER_MANAGEMENT_5, 8, 0),
2547
2548 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
2549 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1430 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2550 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 1431 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
2551 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1432 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2552 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, 1433 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
2553 » » WM8994_POWER_MANAGEMENT_5, 11, 0), 1434 » » WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
2554 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, 1435 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2555 » » WM8994_POWER_MANAGEMENT_5, 10, 0), 1436 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1437 » » WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1438 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2556 1439
2557 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1440 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2558 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1441 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
2559 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1442 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
2560 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1443 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
2561 1444
2562 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1445 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
2563 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1446 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
2564 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1447 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
2565 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1448 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
2566 1449
2567 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1450 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
2568 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1451 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
2569 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1452 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
2570 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1453 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
2571 1454
2572 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1455 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
2573 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1456 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
2574 1457
2575 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1458 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
2576 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1459 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
2577 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1460 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
2578 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1461 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
2579 1462
2580 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1463 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2581 WM8994_POWER_MANAGEMENT_4, 13, 0), 1464 WM8994_POWER_MANAGEMENT_4, 13, 0),
2582 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1465 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2583 WM8994_POWER_MANAGEMENT_4, 12, 0), 1466 WM8994_POWER_MANAGEMENT_4, 12, 0),
2584 SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, 1467 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
2585 » » WM8994_POWER_MANAGEMENT_5, 13, 0), 1468 » » WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
2586 SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, 1469 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2587 » » WM8994_POWER_MANAGEMENT_5, 12, 0), 1470 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1471 » » WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1472 » » SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2588 1473
2589 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1474 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2590 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1475 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1476 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2591 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1477 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2592 1478
2593 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1479 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2594 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1480 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2595 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1481 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2596 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2597 1482
2598 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1483 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2599 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1484 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2600 1485
2601 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1486 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
2602 1487
2603 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1488 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
2604 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1489 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
2605 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1490 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
2606 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1491 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
2607 1492
2608 /* Power is done with the muxes since the ADC power also controls the 1493 /* Power is done with the muxes since the ADC power also controls the
2609 * downsampling chain, the chip will automatically manage the analogue 1494 * downsampling chain, the chip will automatically manage the analogue
2610 * specific portions. 1495 * specific portions.
2611 */ 1496 */
2612 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1497 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
2613 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1498 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
2614 1499
2615 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1500 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
2616 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1501 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
2617 1502
2618 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
2619 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
2620 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
2621 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
2622
2623 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1503 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
2624 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1504 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
2625 1505
2626 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1506 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
2627 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1507 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
2628 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1508 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2629 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1509 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
2630 1510
2631 SND_SOC_DAPM_POST("Debug log", post_ev), 1511 SND_SOC_DAPM_POST("Debug log", post_ev),
2632 }; 1512 };
2633 1513
1514 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1515 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1516 };
1517
1518 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1519 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1520 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1521 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1522 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1523 };
1524
2634 static const struct snd_soc_dapm_route intercon[] = { 1525 static const struct snd_soc_dapm_route intercon[] = {
2635
2636 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1526 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2637 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1527 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2638 1528
2639 { "DSP1CLK", NULL, "CLK_SYS" }, 1529 { "DSP1CLK", NULL, "CLK_SYS" },
2640 { "DSP2CLK", NULL, "CLK_SYS" }, 1530 { "DSP2CLK", NULL, "CLK_SYS" },
2641 { "DSPINTCLK", NULL, "CLK_SYS" }, 1531 { "DSPINTCLK", NULL, "CLK_SYS" },
2642 1532
2643 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1533 { "AIF1ADC1L", NULL, "AIF1CLK" },
2644 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1534 { "AIF1ADC1L", NULL, "DSP1CLK" },
2645 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1535 { "AIF1ADC1R", NULL, "AIF1CLK" },
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after
2733 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1623 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
2734 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1624 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
2735 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1625 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2736 1626
2737 /* Pin level routing for AIF3 */ 1627 /* Pin level routing for AIF3 */
2738 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1628 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
2739 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1629 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
2740 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1630 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2741 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1631 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2742 1632
2743 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2744 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2745
2746 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1633 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2747 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1634 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2748 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1635 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
2749 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1636 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2750 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1637 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
2751 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1638 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
2752 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1639 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
2753 1640
2754 /* DAC1 inputs */ 1641 /* DAC1 inputs */
2755 { "DAC1L", NULL, "DAC1L Mixer" },
2756 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1642 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2757 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1643 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2758 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1644 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2759 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1645 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2760 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1646 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2761 1647
2762 { "DAC1R", NULL, "DAC1R Mixer" },
2763 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1648 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2764 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1649 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2765 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1650 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2766 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1651 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2767 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1652 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2768 1653
2769 /* DAC2/AIF2 outputs */ 1654 /* DAC2/AIF2 outputs */
2770 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1655 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
2771 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2772 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1656 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
2773 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1657 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2774 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1658 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2775 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1659 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2776 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1660 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2777 1661
2778 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1662 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
2779 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2780 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1663 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2781 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1664 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2782 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1665 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2783 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1666 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2784 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1667 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2785 1668
1669 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1670 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1671 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1672 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1673
2786 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1674 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
2787 1675
2788 /* AIF3 output */ 1676 /* AIF3 output */
2789 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1677 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
2790 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1678 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
2791 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1679 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
2792 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1680 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
2793 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1681 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
2794 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1682 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
2795 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1683 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
(...skipping 12 matching lines...) Expand all
2808 { "SPKL", "DAC1 Switch", "DAC1L" }, 1696 { "SPKL", "DAC1 Switch", "DAC1L" },
2809 { "SPKL", "DAC2 Switch", "DAC2L" }, 1697 { "SPKL", "DAC2 Switch", "DAC2L" },
2810 1698
2811 { "SPKR", "DAC1 Switch", "DAC1R" }, 1699 { "SPKR", "DAC1 Switch", "DAC1R" },
2812 { "SPKR", "DAC2 Switch", "DAC2R" }, 1700 { "SPKR", "DAC2 Switch", "DAC2R" },
2813 1701
2814 { "Left Headphone Mux", "DAC", "DAC1L" }, 1702 { "Left Headphone Mux", "DAC", "DAC1L" },
2815 { "Right Headphone Mux", "DAC", "DAC1R" }, 1703 { "Right Headphone Mux", "DAC", "DAC1R" },
2816 }; 1704 };
2817 1705
1706 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1707 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1708 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1709 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1710 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1711 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1712 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1713 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1714 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1715 };
1716
1717 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1718 { "DAC1L", NULL, "DAC1L Mixer" },
1719 { "DAC1R", NULL, "DAC1R Mixer" },
1720 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1721 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1722 };
1723
1724 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1725 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1726 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1727 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1728 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1729 };
1730
1731 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1732 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1733 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1734 };
1735
1736 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1737 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1738 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1739
1740 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1741 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1742 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1743 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1744
1745 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1746 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1747
1748 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1749 };
1750
2818 /* The size in bits of the FLL divide multiplied by 10 1751 /* The size in bits of the FLL divide multiplied by 10
2819 * to allow rounding later */ 1752 * to allow rounding later */
2820 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1753 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2821 1754
2822 struct fll_div { 1755 struct fll_div {
2823 u16 outdiv; 1756 u16 outdiv;
2824 u16 n; 1757 u16 n;
2825 u16 k; 1758 u16 k;
2826 u16 clk_ref_div; 1759 u16 clk_ref_div;
2827 u16 fll_fratio; 1760 u16 fll_fratio;
(...skipping 95 matching lines...) Expand 10 before | Expand all | Expand 10 after
2923 break; 1856 break;
2924 default: 1857 default:
2925 return -EINVAL; 1858 return -EINVAL;
2926 } 1859 }
2927 1860
2928 switch (src) { 1861 switch (src) {
2929 case 0: 1862 case 0:
2930 /* Allow no source specification when stopping */ 1863 /* Allow no source specification when stopping */
2931 if (freq_out) 1864 if (freq_out)
2932 return -EINVAL; 1865 return -EINVAL;
1866 src = wm8994->fll[id].src;
2933 break; 1867 break;
2934 case WM8994_FLL_SRC_MCLK1: 1868 case WM8994_FLL_SRC_MCLK1:
2935 case WM8994_FLL_SRC_MCLK2: 1869 case WM8994_FLL_SRC_MCLK2:
2936 case WM8994_FLL_SRC_LRCLK: 1870 case WM8994_FLL_SRC_LRCLK:
2937 case WM8994_FLL_SRC_BCLK: 1871 case WM8994_FLL_SRC_BCLK:
2938 break; 1872 break;
2939 default: 1873 default:
2940 return -EINVAL; 1874 return -EINVAL;
2941 } 1875 }
2942 1876
(...skipping 144 matching lines...) Expand 10 before | Expand all | Expand 10 after
3087 } 2021 }
3088 2022
3089 configure_clock(codec); 2023 configure_clock(codec);
3090 2024
3091 return 0; 2025 return 0;
3092 } 2026 }
3093 2027
3094 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2028 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3095 enum snd_soc_bias_level level) 2029 enum snd_soc_bias_level level)
3096 { 2030 {
2031 struct wm8994 *control = codec->control_data;
3097 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2032 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3098 2033
3099 switch (level) { 2034 switch (level) {
3100 case SND_SOC_BIAS_ON: 2035 case SND_SOC_BIAS_ON:
3101 break; 2036 break;
3102 2037
3103 case SND_SOC_BIAS_PREPARE: 2038 case SND_SOC_BIAS_PREPARE:
3104 /* VMID=2x40k */ 2039 /* VMID=2x40k */
3105 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2040 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3106 WM8994_VMID_SEL_MASK, 0x2); 2041 WM8994_VMID_SEL_MASK, 0x2);
3107 break; 2042 break;
3108 2043
3109 case SND_SOC_BIAS_STANDBY: 2044 case SND_SOC_BIAS_STANDBY:
3110 » » if (codec->bias_level == SND_SOC_BIAS_OFF) { 2045 » » if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
3111 » » » /* Tweak DC servo and DSP configuration for 2046 » » » pm_runtime_get_sync(codec->dev);
3112 » » » * improved performance. */ 2047
3113 » » » if (wm8994->revision < 4) { 2048 » » » switch (control->type) {
3114 » » » » /* Tweak DC servo and DSP configuration for 2049 » » » case WM8994:
3115 » » » » * improved performance. */ 2050 » » » » if (wm8994->revision < 4) {
3116 » » » » snd_soc_write(codec, 0x102, 0x3); 2051 » » » » » /* Tweak DC servo and DSP
3117 » » » » snd_soc_write(codec, 0x56, 0x3); 2052 » » » » » * configuration for improved
3118 » » » » snd_soc_write(codec, 0x817, 0); 2053 » » » » » * performance. */
3119 » » » » snd_soc_write(codec, 0x102, 0); 2054 » » » » » snd_soc_write(codec, 0x102, 0x3);
2055 » » » » » snd_soc_write(codec, 0x56, 0x3);
2056 » » » » » snd_soc_write(codec, 0x817, 0);
2057 » » » » » snd_soc_write(codec, 0x102, 0);
2058 » » » » }
2059 » » » » break;
2060
2061 » » » case WM8958:
2062 » » » » if (wm8994->revision == 0) {
2063 » » » » » /* Optimise performance for rev A */
2064 » » » » » snd_soc_write(codec, 0x102, 0x3);
2065 » » » » » snd_soc_write(codec, 0xcb, 0x81);
2066 » » » » » snd_soc_write(codec, 0x817, 0);
2067 » » » » » snd_soc_write(codec, 0x102, 0);
2068
2069 » » » » » snd_soc_update_bits(codec,
2070 » » » » » » » WM8958_CHARGE_PUMP_2 ,
2071 » » » » » » » WM8958_CP_DISCH,
2072 » » » » » » » WM8958_CP_DISCH);
2073 » » » » }
2074 » » » » break;
3120 } 2075 }
3121 2076
3122 /* Discharge LINEOUT1 & 2 */ 2077 /* Discharge LINEOUT1 & 2 */
3123 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2078 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
3124 WM8994_LINEOUT1_DISCH | 2079 WM8994_LINEOUT1_DISCH |
3125 WM8994_LINEOUT2_DISCH, 2080 WM8994_LINEOUT2_DISCH,
3126 WM8994_LINEOUT1_DISCH | 2081 WM8994_LINEOUT1_DISCH |
3127 WM8994_LINEOUT2_DISCH); 2082 WM8994_LINEOUT2_DISCH);
3128 2083
3129 /* Startup bias, VMID ramp & buffer */ 2084 /* Startup bias, VMID ramp & buffer */
(...skipping 14 matching lines...) Expand all
3144 msleep(20); 2099 msleep(20);
3145 } 2100 }
3146 2101
3147 /* VMID=2x500k */ 2102 /* VMID=2x500k */
3148 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2103 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3149 WM8994_VMID_SEL_MASK, 0x4); 2104 WM8994_VMID_SEL_MASK, 0x4);
3150 2105
3151 break; 2106 break;
3152 2107
3153 case SND_SOC_BIAS_OFF: 2108 case SND_SOC_BIAS_OFF:
3154 » » if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 2109 » » if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3155 /* Switch over to startup biases */ 2110 /* Switch over to startup biases */
3156 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 2111 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3157 WM8994_BIAS_SRC | 2112 WM8994_BIAS_SRC |
3158 WM8994_STARTUP_BIAS_ENA | 2113 WM8994_STARTUP_BIAS_ENA |
3159 WM8994_VMID_BUF_ENA | 2114 WM8994_VMID_BUF_ENA |
3160 WM8994_VMID_RAMP_MASK, 2115 WM8994_VMID_RAMP_MASK,
3161 WM8994_BIAS_SRC | 2116 WM8994_BIAS_SRC |
3162 WM8994_STARTUP_BIAS_ENA | 2117 WM8994_STARTUP_BIAS_ENA |
3163 WM8994_VMID_BUF_ENA | 2118 WM8994_VMID_BUF_ENA |
3164 (1 << WM8994_VMID_RAMP_SHIFT)); 2119 (1 << WM8994_VMID_RAMP_SHIFT));
(...skipping 11 matching lines...) Expand all
3176 WM8994_LINEOUT2_DISCH); 2131 WM8994_LINEOUT2_DISCH);
3177 2132
3178 msleep(5); 2133 msleep(5);
3179 2134
3180 /* Switch off startup biases */ 2135 /* Switch off startup biases */
3181 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 2136 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3182 WM8994_BIAS_SRC | 2137 WM8994_BIAS_SRC |
3183 WM8994_STARTUP_BIAS_ENA | 2138 WM8994_STARTUP_BIAS_ENA |
3184 WM8994_VMID_BUF_ENA | 2139 WM8994_VMID_BUF_ENA |
3185 WM8994_VMID_RAMP_MASK, 0); 2140 WM8994_VMID_RAMP_MASK, 0);
2141
2142 pm_runtime_put(codec->dev);
3186 } 2143 }
3187 break; 2144 break;
3188 } 2145 }
3189 » codec->bias_level = level; 2146 » codec->dapm.bias_level = level;
3190 return 0; 2147 return 0;
3191 } 2148 }
3192 2149
3193 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2150 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3194 { 2151 {
3195 struct snd_soc_codec *codec = dai->codec; 2152 struct snd_soc_codec *codec = dai->codec;
2153 struct wm8994 *control = codec->control_data;
3196 int ms_reg; 2154 int ms_reg;
3197 int aif1_reg; 2155 int aif1_reg;
3198 int ms = 0; 2156 int ms = 0;
3199 int aif1 = 0; 2157 int aif1 = 0;
3200 2158
3201 switch (dai->id) { 2159 switch (dai->id) {
3202 case 1: 2160 case 1:
3203 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2161 ms_reg = WM8994_AIF1_MASTER_SLAVE;
3204 aif1_reg = WM8994_AIF1_CONTROL_1; 2162 aif1_reg = WM8994_AIF1_CONTROL_1;
3205 break; 2163 break;
(...skipping 64 matching lines...) Expand 10 before | Expand all | Expand 10 after
3270 aif1 |= WM8994_AIF1_LRCLK_INV; 2228 aif1 |= WM8994_AIF1_LRCLK_INV;
3271 break; 2229 break;
3272 default: 2230 default:
3273 return -EINVAL; 2231 return -EINVAL;
3274 } 2232 }
3275 break; 2233 break;
3276 default: 2234 default:
3277 return -EINVAL; 2235 return -EINVAL;
3278 } 2236 }
3279 2237
2238 /* The AIF2 format configuration needs to be mirrored to AIF3
2239 * on WM8958 if it's in use so just do it all the time. */
2240 if (control->type == WM8958 && dai->id == 2)
2241 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2242 WM8994_AIF1_LRCLK_INV |
2243 WM8958_AIF3_FMT_MASK, aif1);
2244
3280 snd_soc_update_bits(codec, aif1_reg, 2245 snd_soc_update_bits(codec, aif1_reg,
3281 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2246 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3282 WM8994_AIF1_FMT_MASK, 2247 WM8994_AIF1_FMT_MASK,
3283 aif1); 2248 aif1);
3284 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2249 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
3285 ms); 2250 ms);
3286 2251
3287 return 0; 2252 return 0;
3288 } 2253 }
3289 2254
(...skipping 20 matching lines...) Expand all
3310 static int bclk_divs[] = { 2275 static int bclk_divs[] = {
3311 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2276 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
3312 640, 880, 960, 1280, 1760, 1920 2277 640, 880, 960, 1280, 1760, 1920
3313 }; 2278 };
3314 2279
3315 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2280 static int wm8994_hw_params(struct snd_pcm_substream *substream,
3316 struct snd_pcm_hw_params *params, 2281 struct snd_pcm_hw_params *params,
3317 struct snd_soc_dai *dai) 2282 struct snd_soc_dai *dai)
3318 { 2283 {
3319 struct snd_soc_codec *codec = dai->codec; 2284 struct snd_soc_codec *codec = dai->codec;
2285 struct wm8994 *control = codec->control_data;
3320 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2286 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3321 int aif1_reg; 2287 int aif1_reg;
2288 int aif2_reg;
3322 int bclk_reg; 2289 int bclk_reg;
3323 int lrclk_reg; 2290 int lrclk_reg;
3324 int rate_reg; 2291 int rate_reg;
3325 int aif1 = 0; 2292 int aif1 = 0;
2293 int aif2 = 0;
3326 int bclk = 0; 2294 int bclk = 0;
3327 int lrclk = 0; 2295 int lrclk = 0;
3328 int rate_val = 0; 2296 int rate_val = 0;
3329 int id = dai->id - 1; 2297 int id = dai->id - 1;
3330 2298
3331 int i, cur_val, best_val, bclk_rate, best; 2299 int i, cur_val, best_val, bclk_rate, best;
3332 2300
3333 switch (dai->id) { 2301 switch (dai->id) {
3334 case 1: 2302 case 1:
3335 aif1_reg = WM8994_AIF1_CONTROL_1; 2303 aif1_reg = WM8994_AIF1_CONTROL_1;
2304 aif2_reg = WM8994_AIF1_CONTROL_2;
3336 bclk_reg = WM8994_AIF1_BCLK; 2305 bclk_reg = WM8994_AIF1_BCLK;
3337 rate_reg = WM8994_AIF1_RATE; 2306 rate_reg = WM8994_AIF1_RATE;
3338 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3339 wm8994->lrclk_shared[0]) { 2308 wm8994->lrclk_shared[0]) {
3340 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2309 lrclk_reg = WM8994_AIF1DAC_LRCLK;
3341 } else { 2310 } else {
3342 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2311 lrclk_reg = WM8994_AIF1ADC_LRCLK;
3343 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2312 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
3344 } 2313 }
3345 break; 2314 break;
3346 case 2: 2315 case 2:
3347 aif1_reg = WM8994_AIF2_CONTROL_1; 2316 aif1_reg = WM8994_AIF2_CONTROL_1;
2317 aif2_reg = WM8994_AIF2_CONTROL_2;
3348 bclk_reg = WM8994_AIF2_BCLK; 2318 bclk_reg = WM8994_AIF2_BCLK;
3349 rate_reg = WM8994_AIF2_RATE; 2319 rate_reg = WM8994_AIF2_RATE;
3350 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3351 wm8994->lrclk_shared[1]) { 2321 wm8994->lrclk_shared[1]) {
3352 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2322 lrclk_reg = WM8994_AIF2DAC_LRCLK;
3353 } else { 2323 } else {
3354 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2324 lrclk_reg = WM8994_AIF2ADC_LRCLK;
3355 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2325 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
3356 } 2326 }
3357 break; 2327 break;
2328 case 3:
2329 switch (control->type) {
2330 case WM8958:
2331 aif1_reg = WM8958_AIF3_CONTROL_1;
2332 break;
2333 default:
2334 return 0;
2335 }
3358 default: 2336 default:
3359 return -EINVAL; 2337 return -EINVAL;
3360 } 2338 }
3361 2339
3362 bclk_rate = params_rate(params) * 2; 2340 bclk_rate = params_rate(params) * 2;
3363 switch (params_format(params)) { 2341 switch (params_format(params)) {
3364 case SNDRV_PCM_FORMAT_S16_LE: 2342 case SNDRV_PCM_FORMAT_S16_LE:
3365 bclk_rate *= 16; 2343 bclk_rate *= 16;
3366 break; 2344 break;
3367 case SNDRV_PCM_FORMAT_S20_3LE: 2345 case SNDRV_PCM_FORMAT_S20_3LE:
(...skipping 17 matching lines...) Expand all
3385 if (srs[i].rate == params_rate(params)) 2363 if (srs[i].rate == params_rate(params))
3386 break; 2364 break;
3387 if (i == ARRAY_SIZE(srs)) 2365 if (i == ARRAY_SIZE(srs))
3388 return -EINVAL; 2366 return -EINVAL;
3389 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2367 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
3390 2368
3391 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2369 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
3392 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2370 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3393 dai->id, wm8994->aifclk[id], bclk_rate); 2371 dai->id, wm8994->aifclk[id], bclk_rate);
3394 2372
2373 if (params_channels(params) == 1 &&
2374 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2375 aif2 |= WM8994_AIF1_MONO;
2376
3395 if (wm8994->aifclk[id] == 0) { 2377 if (wm8994->aifclk[id] == 0) {
3396 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2378 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3397 return -EINVAL; 2379 return -EINVAL;
3398 } 2380 }
3399 2381
3400 /* AIFCLK/fs ratio; look for a close match in either direction */ 2382 /* AIFCLK/fs ratio; look for a close match in either direction */
3401 best = 0; 2383 best = 0;
3402 best_val = abs((fs_ratios[0] * params_rate(params)) 2384 best_val = abs((fs_ratios[0] * params_rate(params))
3403 - wm8994->aifclk[id]); 2385 - wm8994->aifclk[id]);
3404 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2386 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
(...skipping 23 matching lines...) Expand all
3428 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2410 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
3429 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2411 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
3430 bclk_divs[best], bclk_rate); 2412 bclk_divs[best], bclk_rate);
3431 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2413 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
3432 2414
3433 lrclk = bclk_rate / params_rate(params); 2415 lrclk = bclk_rate / params_rate(params);
3434 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2416 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
3435 lrclk, bclk_rate / lrclk); 2417 lrclk, bclk_rate / lrclk);
3436 2418
3437 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2419 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2420 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
3438 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2421 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3439 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2422 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3440 lrclk); 2423 lrclk);
3441 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2424 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
3442 WM8994_AIF1CLK_RATE_MASK, rate_val); 2425 WM8994_AIF1CLK_RATE_MASK, rate_val);
3443 2426
3444 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2427 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3445 switch (dai->id) { 2428 switch (dai->id) {
3446 case 1: 2429 case 1:
3447 wm8994->dac_rates[0] = params_rate(params); 2430 wm8994->dac_rates[0] = params_rate(params);
3448 wm8994_set_retune_mobile(codec, 0); 2431 wm8994_set_retune_mobile(codec, 0);
3449 wm8994_set_retune_mobile(codec, 1); 2432 wm8994_set_retune_mobile(codec, 1);
3450 break; 2433 break;
3451 case 2: 2434 case 2:
3452 wm8994->dac_rates[1] = params_rate(params); 2435 wm8994->dac_rates[1] = params_rate(params);
3453 wm8994_set_retune_mobile(codec, 2); 2436 wm8994_set_retune_mobile(codec, 2);
3454 break; 2437 break;
3455 } 2438 }
3456 } 2439 }
3457 2440
3458 return 0; 2441 return 0;
3459 } 2442 }
3460 2443
2444 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2445 struct snd_pcm_hw_params *params,
2446 struct snd_soc_dai *dai)
2447 {
2448 struct snd_soc_codec *codec = dai->codec;
2449 struct wm8994 *control = codec->control_data;
2450 int aif1_reg;
2451 int aif1 = 0;
2452
2453 switch (dai->id) {
2454 case 3:
2455 switch (control->type) {
2456 case WM8958:
2457 aif1_reg = WM8958_AIF3_CONTROL_1;
2458 break;
2459 default:
2460 return 0;
2461 }
2462 default:
2463 return 0;
2464 }
2465
2466 switch (params_format(params)) {
2467 case SNDRV_PCM_FORMAT_S16_LE:
2468 break;
2469 case SNDRV_PCM_FORMAT_S20_3LE:
2470 aif1 |= 0x20;
2471 break;
2472 case SNDRV_PCM_FORMAT_S24_LE:
2473 aif1 |= 0x40;
2474 break;
2475 case SNDRV_PCM_FORMAT_S32_LE:
2476 aif1 |= 0x60;
2477 break;
2478 default:
2479 return -EINVAL;
2480 }
2481
2482 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2483 }
2484
3461 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2485 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3462 { 2486 {
3463 struct snd_soc_codec *codec = codec_dai->codec; 2487 struct snd_soc_codec *codec = codec_dai->codec;
3464 int mute_reg; 2488 int mute_reg;
3465 int reg; 2489 int reg;
3466 2490
3467 switch (codec_dai->id) { 2491 switch (codec_dai->id) {
3468 case 1: 2492 case 1:
3469 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2493 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3470 break; 2494 break;
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
3505 break; 2529 break;
3506 default: 2530 default:
3507 return -EINVAL; 2531 return -EINVAL;
3508 } 2532 }
3509 2533
3510 if (tristate) 2534 if (tristate)
3511 val = mask; 2535 val = mask;
3512 else 2536 else
3513 val = 0; 2537 val = 0;
3514 2538
3515 » return snd_soc_update_bits(codec, reg, mask, reg); 2539 » return snd_soc_update_bits(codec, reg, mask, val);
3516 } 2540 }
3517 2541
3518 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2542 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3519 2543
3520 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2544 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3521 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2545 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3522 2546
3523 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2547 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3524 .set_sysclk = wm8994_set_dai_sysclk, 2548 .set_sysclk = wm8994_set_dai_sysclk,
3525 .set_fmt = wm8994_set_dai_fmt, 2549 .set_fmt = wm8994_set_dai_fmt,
3526 .hw_params = wm8994_hw_params, 2550 .hw_params = wm8994_hw_params,
3527 .digital_mute = wm8994_aif_mute, 2551 .digital_mute = wm8994_aif_mute,
3528 .set_pll = wm8994_set_fll, 2552 .set_pll = wm8994_set_fll,
3529 .set_tristate = wm8994_set_tristate, 2553 .set_tristate = wm8994_set_tristate,
3530 }; 2554 };
3531 2555
3532 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2556 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3533 .set_sysclk = wm8994_set_dai_sysclk, 2557 .set_sysclk = wm8994_set_dai_sysclk,
3534 .set_fmt = wm8994_set_dai_fmt, 2558 .set_fmt = wm8994_set_dai_fmt,
3535 .hw_params = wm8994_hw_params, 2559 .hw_params = wm8994_hw_params,
3536 .digital_mute = wm8994_aif_mute, 2560 .digital_mute = wm8994_aif_mute,
3537 .set_pll = wm8994_set_fll, 2561 .set_pll = wm8994_set_fll,
3538 .set_tristate = wm8994_set_tristate, 2562 .set_tristate = wm8994_set_tristate,
3539 }; 2563 };
3540 2564
3541 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2565 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2566 .hw_params = wm8994_aif3_hw_params,
3542 .set_tristate = wm8994_set_tristate, 2567 .set_tristate = wm8994_set_tristate,
3543 }; 2568 };
3544 2569
3545 static struct snd_soc_dai_driver wm8994_dai[] = { 2570 static struct snd_soc_dai_driver wm8994_dai[] = {
3546 { 2571 {
3547 .name = "wm8994-aif1", 2572 .name = "wm8994-aif1",
3548 .id = 1, 2573 .id = 1,
3549 .playback = { 2574 .playback = {
3550 .stream_name = "AIF1 Playback", 2575 .stream_name = "AIF1 Playback",
3551 » » » .channels_min = 2, 2576 » » » .channels_min = 1,
3552 .channels_max = 2, 2577 .channels_max = 2,
3553 .rates = WM8994_RATES, 2578 .rates = WM8994_RATES,
3554 .formats = WM8994_FORMATS, 2579 .formats = WM8994_FORMATS,
3555 }, 2580 },
3556 .capture = { 2581 .capture = {
3557 .stream_name = "AIF1 Capture", 2582 .stream_name = "AIF1 Capture",
3558 » » » .channels_min = 2, 2583 » » » .channels_min = 1,
3559 .channels_max = 2, 2584 .channels_max = 2,
3560 .rates = WM8994_RATES, 2585 .rates = WM8994_RATES,
3561 .formats = WM8994_FORMATS, 2586 .formats = WM8994_FORMATS,
3562 }, 2587 },
3563 .ops = &wm8994_aif1_dai_ops, 2588 .ops = &wm8994_aif1_dai_ops,
3564 }, 2589 },
3565 { 2590 {
3566 .name = "wm8994-aif2", 2591 .name = "wm8994-aif2",
3567 .id = 2, 2592 .id = 2,
3568 .playback = { 2593 .playback = {
3569 .stream_name = "AIF2 Playback", 2594 .stream_name = "AIF2 Playback",
3570 » » » .channels_min = 2, 2595 » » » .channels_min = 1,
3571 .channels_max = 2, 2596 .channels_max = 2,
3572 .rates = WM8994_RATES, 2597 .rates = WM8994_RATES,
3573 .formats = WM8994_FORMATS, 2598 .formats = WM8994_FORMATS,
3574 }, 2599 },
3575 .capture = { 2600 .capture = {
3576 .stream_name = "AIF2 Capture", 2601 .stream_name = "AIF2 Capture",
3577 » » » .channels_min = 2, 2602 » » » .channels_min = 1,
3578 .channels_max = 2, 2603 .channels_max = 2,
3579 .rates = WM8994_RATES, 2604 .rates = WM8994_RATES,
3580 .formats = WM8994_FORMATS, 2605 .formats = WM8994_FORMATS,
3581 }, 2606 },
3582 .ops = &wm8994_aif2_dai_ops, 2607 .ops = &wm8994_aif2_dai_ops,
3583 }, 2608 },
3584 { 2609 {
3585 .name = "wm8994-aif3", 2610 .name = "wm8994-aif3",
3586 .id = 3, 2611 .id = 3,
3587 .playback = { 2612 .playback = {
3588 .stream_name = "AIF3 Playback", 2613 .stream_name = "AIF3 Playback",
3589 » » » .channels_min = 2, 2614 » » » .channels_min = 1,
3590 .channels_max = 2, 2615 .channels_max = 2,
3591 .rates = WM8994_RATES, 2616 .rates = WM8994_RATES,
3592 .formats = WM8994_FORMATS, 2617 .formats = WM8994_FORMATS,
3593 }, 2618 },
3594 .capture = { 2619 .capture = {
3595 .stream_name = "AIF3 Capture", 2620 .stream_name = "AIF3 Capture",
3596 » » » .channels_min = 2, 2621 » » » .channels_min = 1,
3597 .channels_max = 2, 2622 .channels_max = 2,
3598 .rates = WM8994_RATES, 2623 .rates = WM8994_RATES,
3599 .formats = WM8994_FORMATS, 2624 .formats = WM8994_FORMATS,
3600 }, 2625 },
3601 .ops = &wm8994_aif3_dai_ops, 2626 .ops = &wm8994_aif3_dai_ops,
3602 } 2627 }
3603 }; 2628 };
3604 2629
3605 #ifdef CONFIG_PM 2630 #ifdef CONFIG_PM
3606 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) 2631 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
(...skipping 11 matching lines...) Expand all
3618 } 2643 }
3619 2644
3620 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 2645 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3621 2646
3622 return 0; 2647 return 0;
3623 } 2648 }
3624 2649
3625 static int wm8994_resume(struct snd_soc_codec *codec) 2650 static int wm8994_resume(struct snd_soc_codec *codec)
3626 { 2651 {
3627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2652 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3628 u16 *reg_cache = codec->reg_cache;
3629 int i, ret; 2653 int i, ret;
2654 unsigned int val, mask;
2655
2656 if (wm8994->revision < 4) {
2657 /* force a HW read */
2658 val = wm8994_reg_read(codec->control_data,
2659 WM8994_POWER_MANAGEMENT_5);
2660
2661 /* modify the cache only */
2662 codec->cache_only = 1;
2663 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2664 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2665 val &= mask;
2666 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2667 mask, val);
2668 codec->cache_only = 0;
2669 }
3630 2670
3631 /* Restore the registers */ 2671 /* Restore the registers */
3632 » for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { 2672 » ret = snd_soc_cache_sync(codec);
3633 » » switch (i) { 2673 » if (ret != 0)
3634 » » case WM8994_LDO_1: 2674 » » dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
3635 » » case WM8994_LDO_2:
3636 » » case WM8994_SOFTWARE_RESET:
3637 » » » /* Handled by other MFD drivers */
3638 » » » continue;
3639 » » default:
3640 » » » break;
3641 » » }
3642
3643 » » if (!access_masks[i].writable)
3644 » » » continue;
3645
3646 » » wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3647 » }
3648 2675
3649 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2676 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3650 2677
3651 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2678 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3652 if (!wm8994->fll_suspend[i].out) 2679 if (!wm8994->fll_suspend[i].out)
3653 continue; 2680 continue;
3654 2681
3655 ret = _wm8994_set_fll(codec, i + 1, 2682 ret = _wm8994_set_fll(codec, i + 1,
3656 wm8994->fll_suspend[i].src, 2683 wm8994->fll_suspend[i].src,
3657 wm8994->fll_suspend[i].in, 2684 wm8994->fll_suspend[i].in,
(...skipping 129 matching lines...) Expand 10 before | Expand all | Expand 10 after
3787 dev_err(wm8994->codec->dev, 2814 dev_err(wm8994->codec->dev,
3788 "Failed to add DRC mode controls: %d\n", ret); 2815 "Failed to add DRC mode controls: %d\n", ret);
3789 2816
3790 for (i = 0; i < WM8994_NUM_DRC; i++) 2817 for (i = 0; i < WM8994_NUM_DRC; i++)
3791 wm8994_set_drc(codec, i); 2818 wm8994_set_drc(codec, i);
3792 } 2819 }
3793 2820
3794 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2821 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3795 pdata->num_retune_mobile_cfgs); 2822 pdata->num_retune_mobile_cfgs);
3796 2823
2824 if (pdata->num_mbc_cfgs) {
2825 struct snd_kcontrol_new control[] = {
2826 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2827 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2828 };
2829
2830 /* We need an array of texts for the enum API */
2831 wm8994->mbc_texts = kmalloc(sizeof(char *)
2832 * pdata->num_mbc_cfgs, GFP_KERNEL);
2833 if (!wm8994->mbc_texts) {
2834 dev_err(wm8994->codec->dev,
2835 "Failed to allocate %d MBC config texts\n",
2836 pdata->num_mbc_cfgs);
2837 return;
2838 }
2839
2840 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2841 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2842
2843 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2844 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2845
2846 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2847 if (ret != 0)
2848 dev_err(wm8994->codec->dev,
2849 "Failed to add MBC mode controls: %d\n", ret);
2850 }
2851
3797 if (pdata->num_retune_mobile_cfgs) 2852 if (pdata->num_retune_mobile_cfgs)
3798 wm8994_handle_retune_mobile_pdata(wm8994); 2853 wm8994_handle_retune_mobile_pdata(wm8994);
3799 else 2854 else
3800 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, 2855 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
3801 ARRAY_SIZE(wm8994_eq_controls)); 2856 ARRAY_SIZE(wm8994_eq_controls));
3802 } 2857 }
3803 2858
3804 /** 2859 /**
3805 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 2860 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3806 * 2861 *
3807 * @codec: WM8994 codec 2862 * @codec: WM8994 codec
3808 * @jack: jack to report detection events on 2863 * @jack: jack to report detection events on
3809 * @micbias: microphone bias to detect on 2864 * @micbias: microphone bias to detect on
3810 * @det: value to report for presence detection 2865 * @det: value to report for presence detection
3811 * @shrt: value to report for short detection 2866 * @shrt: value to report for short detection
3812 * 2867 *
3813 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 2868 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3814 * being used to bring out signals to the processor then only platform 2869 * being used to bring out signals to the processor then only platform
3815 * data configuration is needed for WM8994 and processor GPIOs should 2870 * data configuration is needed for WM8994 and processor GPIOs should
3816 * be configured using snd_soc_jack_add_gpios() instead. 2871 * be configured using snd_soc_jack_add_gpios() instead.
3817 * 2872 *
3818 * Configuration of detection levels is available via the micbias1_lvl 2873 * Configuration of detection levels is available via the micbias1_lvl
3819 * and micbias2_lvl platform data members. 2874 * and micbias2_lvl platform data members.
3820 */ 2875 */
3821 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2876 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3822 int micbias, int det, int shrt) 2877 int micbias, int det, int shrt)
3823 { 2878 {
3824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2879 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3825 struct wm8994_micdet *micdet; 2880 struct wm8994_micdet *micdet;
2881 struct wm8994 *control = codec->control_data;
3826 int reg; 2882 int reg;
3827 2883
2884 if (control->type != WM8994)
2885 return -EINVAL;
2886
3828 switch (micbias) { 2887 switch (micbias) {
3829 case 1: 2888 case 1:
3830 micdet = &wm8994->micdet[0]; 2889 micdet = &wm8994->micdet[0];
3831 break; 2890 break;
3832 case 2: 2891 case 2:
3833 micdet = &wm8994->micdet[1]; 2892 micdet = &wm8994->micdet[1];
3834 break; 2893 break;
3835 default: 2894 default:
3836 return -EINVAL; 2895 return -EINVAL;
3837 } 2896 }
(...skipping 18 matching lines...) Expand all
3856 } 2915 }
3857 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 2916 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3858 2917
3859 static irqreturn_t wm8994_mic_irq(int irq, void *data) 2918 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3860 { 2919 {
3861 struct wm8994_priv *priv = data; 2920 struct wm8994_priv *priv = data;
3862 struct snd_soc_codec *codec = priv->codec; 2921 struct snd_soc_codec *codec = priv->codec;
3863 int reg; 2922 int reg;
3864 int report; 2923 int report;
3865 2924
2925 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2926 trace_snd_soc_jack_irq(dev_name(codec->dev));
2927 #endif
2928
3866 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2929 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3867 if (reg < 0) { 2930 if (reg < 0) {
3868 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2931 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3869 reg); 2932 reg);
3870 return IRQ_HANDLED; 2933 return IRQ_HANDLED;
3871 } 2934 }
3872 2935
3873 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 2936 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3874 2937
3875 report = 0; 2938 report = 0;
3876 if (reg & WM8994_MIC1_DET_STS) 2939 if (reg & WM8994_MIC1_DET_STS)
3877 report |= priv->micdet[0].det; 2940 report |= priv->micdet[0].det;
3878 if (reg & WM8994_MIC1_SHRT_STS) 2941 if (reg & WM8994_MIC1_SHRT_STS)
3879 report |= priv->micdet[0].shrt; 2942 report |= priv->micdet[0].shrt;
3880 snd_soc_jack_report(priv->micdet[0].jack, report, 2943 snd_soc_jack_report(priv->micdet[0].jack, report,
3881 priv->micdet[0].det | priv->micdet[0].shrt); 2944 priv->micdet[0].det | priv->micdet[0].shrt);
3882 2945
3883 report = 0; 2946 report = 0;
3884 if (reg & WM8994_MIC2_DET_STS) 2947 if (reg & WM8994_MIC2_DET_STS)
3885 report |= priv->micdet[1].det; 2948 report |= priv->micdet[1].det;
3886 if (reg & WM8994_MIC2_SHRT_STS) 2949 if (reg & WM8994_MIC2_SHRT_STS)
3887 report |= priv->micdet[1].shrt; 2950 report |= priv->micdet[1].shrt;
3888 snd_soc_jack_report(priv->micdet[1].jack, report, 2951 snd_soc_jack_report(priv->micdet[1].jack, report,
3889 priv->micdet[1].det | priv->micdet[1].shrt); 2952 priv->micdet[1].det | priv->micdet[1].shrt);
3890 2953
3891 return IRQ_HANDLED; 2954 return IRQ_HANDLED;
3892 } 2955 }
3893 2956
2957 /* Default microphone detection handler for WM8958 - the user can
2958 * override this if they wish.
2959 */
2960 static void wm8958_default_micdet(u16 status, void *data)
2961 {
2962 struct snd_soc_codec *codec = data;
2963 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2964 int report = 0;
2965
2966 /* If nothing present then clear our statuses */
2967 if (!(status & WM8958_MICD_STS)) {
2968 wm8994->jack_is_video = false;
2969 wm8994->jack_is_mic = false;
2970 goto done;
2971 }
2972
2973 /* Assume anything over 475 ohms is a microphone and remember
2974 * that we've seen one (since buttons override it) */
2975 if (status & 0x600)
2976 wm8994->jack_is_mic = true;
2977 if (wm8994->jack_is_mic)
2978 report |= SND_JACK_MICROPHONE;
2979
2980 /* Video has an impedence of approximately 75 ohms; assume
2981 * this isn't used as a button and remember it since buttons
2982 * override it. */
2983 if (status & 0x40)
2984 wm8994->jack_is_video = true;
2985 if (wm8994->jack_is_video)
2986 report |= SND_JACK_VIDEOOUT;
2987
2988 /* Everything else is buttons; just assign slots */
2989 if (status & 0x4)
2990 report |= SND_JACK_BTN_0;
2991 if (status & 0x8)
2992 report |= SND_JACK_BTN_1;
2993 if (status & 0x10)
2994 report |= SND_JACK_BTN_2;
2995 if (status & 0x20)
2996 report |= SND_JACK_BTN_3;
2997 if (status & 0x80)
2998 report |= SND_JACK_BTN_4;
2999 if (status & 0x100)
3000 report |= SND_JACK_BTN_5;
3001
3002 done:
3003 snd_soc_jack_report(wm8994->micdet[0].jack,
3004 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
3005 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
3006 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
3007 report);
3008 }
3009
3010 /**
3011 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3012 *
3013 * @codec: WM8958 codec
3014 * @jack: jack to report detection events on
3015 *
3016 * Enable microphone detection functionality for the WM8958. By
3017 * default simple detection which supports the detection of up to 6
3018 * buttons plus video and microphone functionality is supported.
3019 *
3020 * The WM8958 has an advanced jack detection facility which is able to
3021 * support complex accessory detection, especially when used in
3022 * conjunction with external circuitry. In order to provide maximum
3023 * flexiblity a callback is provided which allows a completely custom
3024 * detection algorithm.
3025 */
3026 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3027 wm8958_micdet_cb cb, void *cb_data)
3028 {
3029 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3030 struct wm8994 *control = codec->control_data;
3031
3032 if (control->type != WM8958)
3033 return -EINVAL;
3034
3035 if (jack) {
3036 if (!cb) {
3037 dev_dbg(codec->dev, "Using default micdet callback\n");
3038 cb = wm8958_default_micdet;
3039 cb_data = codec;
3040 }
3041
3042 wm8994->micdet[0].jack = jack;
3043 wm8994->jack_cb = cb;
3044 wm8994->jack_cb_data = cb_data;
3045
3046 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3047 WM8958_MICD_ENA, WM8958_MICD_ENA);
3048 } else {
3049 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3050 WM8958_MICD_ENA, 0);
3051 }
3052
3053 return 0;
3054 }
3055 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3056
3057 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3058 {
3059 struct wm8994_priv *wm8994 = data;
3060 struct snd_soc_codec *codec = wm8994->codec;
3061 int reg;
3062
3063 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3064 if (reg < 0) {
3065 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3066 reg);
3067 return IRQ_NONE;
3068 }
3069
3070 if (!(reg & WM8958_MICD_VALID)) {
3071 dev_dbg(codec->dev, "Mic detect data not valid\n");
3072 goto out;
3073 }
3074
3075 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3076 trace_snd_soc_jack_irq(dev_name(codec->dev));
3077 #endif
3078
3079 if (wm8994->jack_cb)
3080 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3081 else
3082 dev_warn(codec->dev, "Accessory detection with no callback\n");
3083
3084 out:
3085 return IRQ_HANDLED;
3086 }
3087
3894 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3088 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3895 { 3089 {
3090 struct wm8994 *control;
3896 struct wm8994_priv *wm8994; 3091 struct wm8994_priv *wm8994;
3092 struct snd_soc_dapm_context *dapm = &codec->dapm;
3897 int ret, i; 3093 int ret, i;
3898 3094
3899 codec->control_data = dev_get_drvdata(codec->dev->parent); 3095 codec->control_data = dev_get_drvdata(codec->dev->parent);
3096 control = codec->control_data;
3900 3097
3901 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 3098 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3902 if (wm8994 == NULL) 3099 if (wm8994 == NULL)
3903 return -ENOMEM; 3100 return -ENOMEM;
3904 snd_soc_codec_set_drvdata(codec, wm8994); 3101 snd_soc_codec_set_drvdata(codec, wm8994);
3905 3102
3906 codec->reg_cache = &wm8994->reg_cache;
3907
3908 wm8994->pdata = dev_get_platdata(codec->dev->parent); 3103 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3909 wm8994->codec = codec; 3104 wm8994->codec = codec;
3910 3105
3911 » /* Fill the cache with physical values we inherited; don't reset */ 3106 » pm_runtime_enable(codec->dev);
3912 » ret = wm8994_bulk_read(codec->control_data, 0, 3107 » pm_runtime_resume(codec->dev);
3913 » » » ARRAY_SIZE(wm8994->reg_cache) - 1, 3108
3914 » » » codec->reg_cache); 3109 » /* Read our current status back from the chip - we don't want to
3915 » if (ret < 0) { 3110 » * reset as this may interfere with the GPIO or LDO operation. */
3916 » » dev_err(codec->dev, "Failed to fill register cache: %d\n", 3111 » for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3917 » » » ret); 3112 » » if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3918 » » goto err; 3113 » » » continue;
3919 » } 3114
3920 3115 » » ret = wm8994_reg_read(codec->control_data, i);
3921 » /* Clear the cached values for unreadable/volatile registers to 3116 » » if (ret <= 0)
3922 » * avoid potential confusion. 3117 » » » continue;
3923 » */ 3118
3924 » for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) 3119 » » ret = snd_soc_cache_write(codec, i, ret);
3925 » » if (wm8994_volatile(i) || !wm8994_readable(i)) 3120 » » if (ret != 0) {
3926 » » » wm8994->reg_cache[i] = 0; 3121 » » » dev_err(codec->dev,
3122 » » » » "Failed to initialise cache for 0x%x: %d\n",
3123 » » » » i, ret);
3124 » » » goto err;
3125 » » }
3126 » }
3927 3127
3928 /* Set revision-specific configuration */ 3128 /* Set revision-specific configuration */
3929 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 3129 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3930 » switch (wm8994->revision) { 3130 » switch (control->type) {
3931 » case 2: 3131 » case WM8994:
3932 » case 3: 3132 » » switch (wm8994->revision) {
3933 » » wm8994->hubs.dcs_codes = -5; 3133 » » case 2:
3934 » » wm8994->hubs.hp_startup_mode = 1; 3134 » » case 3:
3135 » » » wm8994->hubs.dcs_codes = -5;
3136 » » » wm8994->hubs.hp_startup_mode = 1;
3137 » » » wm8994->hubs.dcs_readback_mode = 1;
3138 » » » break;
3139 » » default:
3140 » » » wm8994->hubs.dcs_readback_mode = 1;
3141 » » » break;
3142 » » }
3143
3144 » case WM8958:
3935 wm8994->hubs.dcs_readback_mode = 1; 3145 wm8994->hubs.dcs_readback_mode = 1;
3936 break; 3146 break;
3147
3937 default: 3148 default:
3938 » » wm8994->hubs.dcs_readback_mode = 1; 3149 » » break;
3939 » » break; 3150 » }
3940 » } 3151
3941 3152 » switch (control->type) {
3942 » ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3153 » case WM8994:
3943 » » » » wm8994_mic_irq, "Mic 1 detect", wm8994); 3154 » » ret = wm8994_request_irq(codec->control_data,
3944 » if (ret != 0) 3155 » » » » » WM8994_IRQ_MIC1_DET,
3945 » » dev_warn(codec->dev, 3156 » » » » » wm8994_mic_irq, "Mic 1 detect",
3946 » » » "Failed to request Mic1 detect IRQ: %d\n", ret); 3157 » » » » » wm8994);
3947 3158 » » if (ret != 0)
3948 » ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 3159 » » » dev_warn(codec->dev,
3949 » » » » wm8994_mic_irq, "Mic 1 short", wm8994); 3160 » » » » "Failed to request Mic1 detect IRQ: %d\n",
3950 » if (ret != 0) 3161 » » » » ret);
3951 » » dev_warn(codec->dev, 3162
3952 » » » "Failed to request Mic1 short IRQ: %d\n", ret); 3163 » » ret = wm8994_request_irq(codec->control_data,
3953 3164 » » » » » WM8994_IRQ_MIC1_SHRT,
3954 » ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 3165 » » » » » wm8994_mic_irq, "Mic 1 short",
3955 » » » » wm8994_mic_irq, "Mic 2 detect", wm8994); 3166 » » » » » wm8994);
3956 » if (ret != 0) 3167 » » if (ret != 0)
3957 » » dev_warn(codec->dev, 3168 » » » dev_warn(codec->dev,
3958 » » » "Failed to request Mic2 detect IRQ: %d\n", ret); 3169 » » » » "Failed to request Mic1 short IRQ: %d\n",
3959 3170 » » » » ret);
3960 » ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3171
3961 » » » » wm8994_mic_irq, "Mic 2 short", wm8994); 3172 » » ret = wm8994_request_irq(codec->control_data,
3962 » if (ret != 0) 3173 » » » » » WM8994_IRQ_MIC2_DET,
3963 » » dev_warn(codec->dev, 3174 » » » » » wm8994_mic_irq, "Mic 2 detect",
3964 » » » "Failed to request Mic2 short IRQ: %d\n", ret); 3175 » » » » » wm8994);
3176 » » if (ret != 0)
3177 » » » dev_warn(codec->dev,
3178 » » » » "Failed to request Mic2 detect IRQ: %d\n",
3179 » » » » ret);
3180
3181 » » ret = wm8994_request_irq(codec->control_data,
3182 » » » » » WM8994_IRQ_MIC2_SHRT,
3183 » » » » » wm8994_mic_irq, "Mic 2 short",
3184 » » » » » wm8994);
3185 » » if (ret != 0)
3186 » » » dev_warn(codec->dev,
3187 » » » » "Failed to request Mic2 short IRQ: %d\n",
3188 » » » » ret);
3189 » » break;
3190
3191 » case WM8958:
3192 » » ret = wm8994_request_irq(codec->control_data,
3193 » » » » » WM8994_IRQ_MIC1_DET,
3194 » » » » » wm8958_mic_irq, "Mic detect",
3195 » » » » » wm8994);
3196 » » if (ret != 0)
3197 » » » dev_warn(codec->dev,
3198 » » » » "Failed to request Mic detect IRQ: %d\n",
3199 » » » » ret);
3200 » » break;
3201 » }
3965 3202
3966 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3203 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3967 * configured on init - if a system wants to do this dynamically 3204 * configured on init - if a system wants to do this dynamically
3968 * at runtime we can deal with that then. 3205 * at runtime we can deal with that then.
3969 */ 3206 */
3970 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); 3207 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3971 if (ret < 0) { 3208 if (ret < 0) {
3972 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 3209 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3973 goto err_irq; 3210 goto err_irq;
3974 } 3211 }
(...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after
4027 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 3264 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4028 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 3265 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4029 3266
4030 wm8994_update_class_w(codec); 3267 wm8994_update_class_w(codec);
4031 3268
4032 wm8994_handle_pdata(wm8994); 3269 wm8994_handle_pdata(wm8994);
4033 3270
4034 wm_hubs_add_analogue_controls(codec); 3271 wm_hubs_add_analogue_controls(codec);
4035 snd_soc_add_controls(codec, wm8994_snd_controls, 3272 snd_soc_add_controls(codec, wm8994_snd_controls,
4036 ARRAY_SIZE(wm8994_snd_controls)); 3273 ARRAY_SIZE(wm8994_snd_controls));
4037 » snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, 3274 » snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4038 ARRAY_SIZE(wm8994_dapm_widgets)); 3275 ARRAY_SIZE(wm8994_dapm_widgets));
3276
3277 switch (control->type) {
3278 case WM8994:
3279 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3280 ARRAY_SIZE(wm8994_specific_dapm_widget s));
3281 if (wm8994->revision < 4) {
3282 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widg ets,
3283 ARRAY_SIZE(wm8994_lateclk_revd _widgets));
3284 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3285 ARRAY_SIZE(wm8994_dac_revd_wid gets));
3286 } else {
3287 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3288 ARRAY_SIZE(wm8994_lateclk_widg ets));
3289 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3290 ARRAY_SIZE(wm8994_dac_widgets) );
3291 }
3292 break;
3293 case WM8958:
3294 snd_soc_add_controls(codec, wm8958_snd_controls,
3295 ARRAY_SIZE(wm8958_snd_controls));
3296 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3297 ARRAY_SIZE(wm8958_dapm_widgets));
3298 break;
3299 }
3300
3301
4039 wm_hubs_add_analogue_routes(codec, 0, 0); 3302 wm_hubs_add_analogue_routes(codec, 0, 0);
4040 » snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 3303 » snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3304
3305 » switch (control->type) {
3306 » case WM8994:
3307 » » snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3308 » » » » » ARRAY_SIZE(wm8994_intercon));
3309
3310 » » if (wm8994->revision < 4) {
3311 » » » snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3312 » » » » » » ARRAY_SIZE(wm8994_revd_intercon) );
3313 » » » snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_interc on,
3314 » » » » » » ARRAY_SIZE(wm8994_lateclk_revd_i ntercon));
3315 » » } else {
3316 » » » snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3317 » » » » » » ARRAY_SIZE(wm8994_lateclk_interc on));
3318 » » }
3319 » » break;
3320 » case WM8958:
3321 » » snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3322 » » » » » ARRAY_SIZE(wm8958_intercon));
3323 » » break;
3324 » }
4041 3325
4042 return 0; 3326 return 0;
4043 3327
4044 err_irq: 3328 err_irq:
4045 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3329 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
4046 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3330 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
4047 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3331 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
4048 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3332 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
4049 err: 3333 err:
4050 kfree(wm8994); 3334 kfree(wm8994);
4051 return ret; 3335 return ret;
4052 } 3336 }
4053 3337
4054 static int wm8994_codec_remove(struct snd_soc_codec *codec) 3338 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4055 { 3339 {
4056 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3340 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3341 struct wm8994 *control = codec->control_data;
4057 3342
4058 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3343 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4059 3344
4060 » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3345 » pm_runtime_disable(codec->dev);
4061 » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3346
4062 » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3347 » switch (control->type) {
4063 » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3348 » case WM8994:
3349 » » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3350 » » » » wm8994);
3351 » » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3352 » » » » wm8994);
3353 » » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3354 » » » » wm8994);
3355 » » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3356 » » » » wm8994);
3357 » » break;
3358
3359 » case WM8958:
3360 » » wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3361 » » » » wm8994);
3362 » » break;
3363 » }
4064 kfree(wm8994->retune_mobile_texts); 3364 kfree(wm8994->retune_mobile_texts);
4065 kfree(wm8994->drc_texts); 3365 kfree(wm8994->drc_texts);
4066 kfree(wm8994); 3366 kfree(wm8994);
4067 3367
4068 return 0; 3368 return 0;
4069 } 3369 }
4070 3370
4071 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 3371 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4072 .probe = wm8994_codec_probe, 3372 .probe = wm8994_codec_probe,
4073 .remove = wm8994_codec_remove, 3373 .remove = wm8994_codec_remove,
4074 .suspend = wm8994_suspend, 3374 .suspend = wm8994_suspend,
4075 .resume = wm8994_resume, 3375 .resume = wm8994_resume,
4076 » .read = wm8994_read, 3376 » .read =»» wm8994_read,
4077 » .write = wm8994_write, 3377 » .write =» wm8994_write,
4078 .readable_register = wm8994_readable, 3378 .readable_register = wm8994_readable,
4079 .volatile_register = wm8994_volatile, 3379 .volatile_register = wm8994_volatile,
4080 .set_bias_level = wm8994_set_bias_level, 3380 .set_bias_level = wm8994_set_bias_level,
3381
3382 .reg_cache_size = WM8994_CACHE_SIZE,
3383 .reg_cache_default = wm8994_reg_defaults,
3384 .reg_word_size = 2,
3385 .compress_type = SND_SOC_RBTREE_COMPRESSION,
4081 }; 3386 };
4082 3387
4083 static int __devinit wm8994_probe(struct platform_device *pdev) 3388 static int __devinit wm8994_probe(struct platform_device *pdev)
4084 { 3389 {
4085 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 3390 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4086 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3391 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4087 } 3392 }
4088 3393
4089 static int __devexit wm8994_remove(struct platform_device *pdev) 3394 static int __devexit wm8994_remove(struct platform_device *pdev)
4090 { 3395 {
(...skipping 20 matching lines...) Expand all
4111 { 3416 {
4112 platform_driver_unregister(&wm8994_codec_driver); 3417 platform_driver_unregister(&wm8994_codec_driver);
4113 } 3418 }
4114 module_exit(wm8994_exit); 3419 module_exit(wm8994_exit);
4115 3420
4116 3421
4117 MODULE_DESCRIPTION("ASoC WM8994 driver"); 3422 MODULE_DESCRIPTION("ASoC WM8994 driver");
4118 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3423 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4119 MODULE_LICENSE("GPL"); 3424 MODULE_LICENSE("GPL");
4120 MODULE_ALIAS("platform:wm8994-codec"); 3425 MODULE_ALIAS("platform:wm8994-codec");
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