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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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193 const int Register::kRegisterCodeByAllocationIndex[kNumAllocatableRegisters] = { | 193 const int Register::kRegisterCodeByAllocationIndex[kNumAllocatableRegisters] = { |
194 // rax, rbx, rdx, rcx, rdi, r8, r9, r11, r14, r12 | 194 // rax, rbx, rdx, rcx, rdi, r8, r9, r11, r14, r12 |
195 0, 3, 2, 1, 7, 8, 9, 11, 14, 12 | 195 0, 3, 2, 1, 7, 8, 9, 11, 14, 12 |
196 }; | 196 }; |
197 | 197 |
198 const int Register::kAllocationIndexByRegisterCode[kNumRegisters] = { | 198 const int Register::kAllocationIndexByRegisterCode[kNumRegisters] = { |
199 0, 3, 2, 1, -1, -1, -1, 4, 5, 6, -1, 7, 9, -1, 8, -1 | 199 0, 3, 2, 1, -1, -1, -1, 4, 5, 6, -1, 7, 9, -1, 8, -1 |
200 }; | 200 }; |
201 | 201 |
202 | 202 |
203 const int Register::kRspIndexForPushAllByRegisterCode[kNumRegisters] = { | |
204 10, 9, 8, 7, -1, -1, 6, 5, 4, 3, -1, 2, 1, -1, 0, -1 | |
205 }; | |
206 | |
207 | |
208 // ----------------------------------------------------------------------------- | 203 // ----------------------------------------------------------------------------- |
209 // Implementation of Operand | 204 // Implementation of Operand |
210 | 205 |
211 Operand::Operand(Register base, int32_t disp) : rex_(0) { | 206 Operand::Operand(Register base, int32_t disp) : rex_(0) { |
212 len_ = 1; | 207 len_ = 1; |
213 if (base.is(rsp) || base.is(r12)) { | 208 if (base.is(rsp) || base.is(r12)) { |
214 // SIB byte is needed to encode (rsp + offset) or (r12 + offset). | 209 // SIB byte is needed to encode (rsp + offset) or (r12 + offset). |
215 set_sib(times_1, rsp, base); | 210 set_sib(times_1, rsp, base); |
216 } | 211 } |
217 | 212 |
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3136 // specially coded on x64 means that it is a relative 32 bit address, as used | 3131 // specially coded on x64 means that it is a relative 32 bit address, as used |
3137 // by branch instructions. | 3132 // by branch instructions. |
3138 return (1 << rmode_) & kApplyMask; | 3133 return (1 << rmode_) & kApplyMask; |
3139 } | 3134 } |
3140 | 3135 |
3141 | 3136 |
3142 | 3137 |
3143 } } // namespace v8::internal | 3138 } } // namespace v8::internal |
3144 | 3139 |
3145 #endif // V8_TARGET_ARCH_X64 | 3140 #endif // V8_TARGET_ARCH_X64 |
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